Commit graph

9 commits

Author SHA1 Message Date
cinap_lenrek 548a48d156 imx8: pcie and nvme support 2022-07-03 11:36:50 +00:00
cinap_lenrek 78c7ad88ff kernel: add extra negative and power-of-two check to pcibarsize() 2021-11-26 21:47:15 +00:00
cinap_lenrek 20ea113790 kernel: support large 64-bit pci membars, increase pc64 VMAPSIZE to 1TB
This makes vmap()/vunmap() take a vlong size argument,
and change the type of Pci.mem[].size to vlong as well.

Even if vmap() wont support large mappings, it is nice to
get the original unruncated value for error checking.

pc64 needs a bigger VMAP window, as system76 pangolin
puts the framebuffer at a physical address > 512GB.
2021-11-26 20:51:45 +00:00
cinap_lenrek c3589ef3cf kernel: export pcienumcaps() for custom capability enumeration in drivers (virtio)
This used to be a internal function, but virtio
uses multiple structures with the same cap type
to indicate the location of various register
blocks in the pci bars so export it.
2021-07-10 18:34:22 +00:00
cinap_lenrek 7c62c12701 kernel: use 64-bit mask to avoid compiler warning in port/pci.c 2021-03-13 14:20:00 +01:00
cinap_lenrek a0404ff582 devpccard, pci: fix pccard support and handle pci expansion roms
let pci.c deal with the special cardbus controller bar0 and
expansion roms.

handle apic interrupt routing for devices behind a cardbus slot.

do not free the pcidev on card removal, as the drivers
most certanly are not prepared to handle this yet.
instead, we provide a pcidevfree() function that just unlinks
the device from pcilist and the parent bridge.
2021-03-01 17:24:54 +01:00
cinap_lenrek 1376d39ef1 kernel: add portable pcimsienable()/pcimsidisable(), disable MSI/MSI-X on pcidisable()/pcireset()
This avoids some duplication in the pci support code and
allows pcireset() to diable MSI and MSI-X interrupts
when disabling or reseting a device.
2020-11-21 16:02:21 +01:00
cinap_lenrek da54e4bfc2 kernel: remove unused pcinextcap() function 2020-11-21 00:41:57 +01:00
cinap_lenrek 4f85115526 kernel: massive pci code rewrite
The new pci code is moved to port/pci.[hc] and shared by
all ports.

Each port has its own PCI controller implementation,
providing the pcicfgrw*() functions for low level pci
config space access. The locking for pcicfgrw*() is now
done by the caller (only port/pci.c).

Device drivers now need to include "../port/pci.h" in
addition to "io.h".

The new code now checks bridge windows and membars,
while enumerating the bus, giving the pc driver a chance
to re-assign them. This is needed because some UEFI
implementations fail to assign the bars for some devices,
so we need to do it outselfs. (See pcireservemem()).

While working on this, it was discovered that the pci
code assimed the smallest I/O bar size is 16 (pcibarsize()),
which is wrong. I/O bars can be as small as 4 bytes.
Bit 1 in an I/O bar is also reserved and should be masked off,
making the port mask: port = bar & ~3;
2020-09-13 20:33:17 +02:00
Renamed from sys/src/9/bcm64/pci.c (Browse further)