kw: use ethermii.c from port/ (thanks stuart)
This commit is contained in:
cinap_lenrek
parent
809a7402fc
commit
f11526708e
4 changed files with 32 additions and 380 deletions
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@ -18,7 +18,7 @@
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#include "../port/netif.h"
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#include "../port/etherif.h"
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#include "ethermii.h"
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#include "../port/ethermii.h"
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#include "../ip/ip.h"
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#define MIIDBG if(0)iprint
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@ -363,6 +363,36 @@ enum {
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SmiRegaddrmask = 0x1f << SmiRegaddroff,
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};
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enum {
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/* 88e1116-specific paged registers */
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Scr = 16, /* special control register */
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Ssr = 17, /* special status register */
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Ier = 18, /* interrupt enable reg */
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Isr = 19, /* interrupt status reg */
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Escr = 20, /* extended special control reg */
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Recr = 21, /* RX error counter reg */
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Eadr = 22, /* extended address reg (page select) */
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Globsts = 23, /* global status */
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Impover = 24, /* RGMII output impedance override (page 2) */
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Imptarg = 25, /* RGMII output impedance target (page 2) */
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Scr2 = 26, /* special control register 2 */
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};
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enum { /* Scr page 0 */
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Pwrdown = 0x0004, /* power down */
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Mdix = 0x0060, /* MDI crossover mode */
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Endetect = 0x0300, /* energy detect */
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};
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enum { /* Scr page 2 */
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Rgmiipwrup = 0x0008, /* RGMII power up: must sw reset after */
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};
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enum { /* Recr page 2 */
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Txtiming = 1<<4,
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Rxtiming = 1<<5,
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};
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struct Gbereg {
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ulong phy; /* PHY address */
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ulong smi; /* serial mgmt. interface */
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@ -1,235 +0,0 @@
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "../port/etherif.h"
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#include "ethermii.h"
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int
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mii(Mii* mii, int mask)
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{
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MiiPhy *miiphy;
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int bit, oui, phyno, r, rmask;
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/*
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* Probe through mii for PHYs in mask;
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* return the mask of those found in the current probe.
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* If the PHY has not already been probed, update
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* the Mii information.
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*/
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rmask = 0;
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for(phyno = 0; phyno < NMiiPhy; phyno++){
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bit = 1<<phyno;
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if(!(mask & bit))
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continue;
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if(mii->mask & bit){
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rmask |= bit;
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continue;
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}
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if(mii->mir(mii, phyno, Bmsr) == -1)
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continue;
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r = mii->mir(mii, phyno, Phyidr1);
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oui = (r & 0x3FFF)<<6;
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r = mii->mir(mii, phyno, Phyidr2);
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oui |= r>>10;
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if(oui == 0xFFFFF || oui == 0)
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continue;
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if((miiphy = malloc(sizeof(MiiPhy))) == nil)
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continue;
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miiphy->mii = mii;
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miiphy->oui = oui;
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miiphy->phyno = phyno;
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miiphy->anar = ~0;
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miiphy->fc = ~0;
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miiphy->mscr = ~0;
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mii->phy[phyno] = miiphy;
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if(mii->curphy == nil)
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mii->curphy = miiphy;
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mii->mask |= bit;
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mii->nphy++;
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rmask |= bit;
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}
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return rmask;
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}
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int
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miimir(Mii* mii, int r)
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{
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if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
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return -1;
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return mii->mir(mii, mii->curphy->phyno, r);
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}
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int
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miimiw(Mii* mii, int r, int data)
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{
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if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
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return -1;
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return mii->miw(mii, mii->curphy->phyno, r, data);
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}
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int
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miireset(Mii* mii)
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{
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int bmcr;
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if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
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return -1;
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bmcr = mii->mir(mii, mii->curphy->phyno, Bmcr);
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bmcr |= BmcrR;
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mii->miw(mii, mii->curphy->phyno, Bmcr, bmcr);
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microdelay(1);
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return 0;
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}
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int
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miiane(Mii* mii, int a, int p, int e)
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{
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int anar, bmsr, mscr, r, phyno;
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if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
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return -1;
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phyno = mii->curphy->phyno;
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bmsr = mii->mir(mii, phyno, Bmsr);
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if(!(bmsr & BmsrAna))
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return -1;
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if(a != ~0)
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anar = (AnaTXFD|AnaTXHD|Ana10FD|Ana10HD) & a;
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else if(mii->curphy->anar != ~0)
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anar = mii->curphy->anar;
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else{
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anar = mii->mir(mii, phyno, Anar);
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anar &= ~(AnaAP|AnaP|AnaT4|AnaTXFD|AnaTXHD|Ana10FD|Ana10HD);
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if(bmsr & Bmsr10THD)
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anar |= Ana10HD;
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if(bmsr & Bmsr10TFD)
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anar |= Ana10FD;
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if(bmsr & Bmsr100TXHD)
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anar |= AnaTXHD;
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if(bmsr & Bmsr100TXFD)
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anar |= AnaTXFD;
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}
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mii->curphy->anar = anar;
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if(p != ~0)
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anar |= (AnaAP|AnaP) & p;
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else if(mii->curphy->fc != ~0)
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anar |= mii->curphy->fc;
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mii->curphy->fc = (AnaAP|AnaP) & anar;
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if(bmsr & BmsrEs){
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mscr = mii->mir(mii, phyno, Mscr);
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mscr &= ~(Mscr1000TFD|Mscr1000THD);
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if(e != ~0)
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mscr |= (Mscr1000TFD|Mscr1000THD) & e;
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else if(mii->curphy->mscr != ~0)
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mscr = mii->curphy->mscr;
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else{
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r = mii->mir(mii, phyno, Esr);
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if(r & Esr1000THD)
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mscr |= Mscr1000THD;
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if(r & Esr1000TFD)
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mscr |= Mscr1000TFD;
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}
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mii->curphy->mscr = mscr;
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mii->miw(mii, phyno, Mscr, mscr);
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}
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mii->miw(mii, phyno, Anar, anar);
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r = mii->mir(mii, phyno, Bmcr);
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if(!(r & BmcrR)){
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r |= BmcrAne|BmcrRan;
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mii->miw(mii, phyno, Bmcr, r);
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}
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return 0;
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}
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int
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miistatus(Mii* mii)
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{
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MiiPhy *phy;
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int anlpar, bmsr, p, r, phyno;
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if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
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return -1;
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phy = mii->curphy;
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phyno = phy->phyno;
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/*
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* Check Auto-Negotiation is complete and link is up.
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* (Read status twice as the Ls bit is sticky).
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*/
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bmsr = mii->mir(mii, phyno, Bmsr);
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if(!(bmsr & (BmsrAnc|BmsrAna))) {
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// print("miistatus: auto-neg incomplete\n");
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return -1;
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}
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bmsr = mii->mir(mii, phyno, Bmsr);
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if(!(bmsr & BmsrLs)){
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// print("miistatus: link down\n");
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phy->link = 0;
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return -1;
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}
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phy->speed = phy->fd = phy->rfc = phy->tfc = 0;
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if(phy->mscr){
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r = mii->mir(mii, phyno, Mssr);
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if((phy->mscr & Mscr1000TFD) && (r & Mssr1000TFD)){
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phy->speed = 1000;
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phy->fd = 1;
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}
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else if((phy->mscr & Mscr1000THD) && (r & Mssr1000THD))
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phy->speed = 1000;
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}
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anlpar = mii->mir(mii, phyno, Anlpar);
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if(phy->speed == 0){
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r = phy->anar & anlpar;
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if(r & AnaTXFD){
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phy->speed = 100;
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phy->fd = 1;
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}
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else if(r & AnaTXHD)
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phy->speed = 100;
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else if(r & Ana10FD){
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phy->speed = 10;
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phy->fd = 1;
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}
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else if(r & Ana10HD)
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phy->speed = 10;
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}
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if(phy->speed == 0) {
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// print("miistatus: phy speed 0\n");
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return -1;
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}
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if(phy->fd){
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p = phy->fc;
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r = anlpar & (AnaAP|AnaP);
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if(p == AnaAP && r == (AnaAP|AnaP))
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phy->tfc = 1;
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else if(p == (AnaAP|AnaP) && r == AnaAP)
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phy->rfc = 1;
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else if((p & AnaP) && (r & AnaP))
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phy->rfc = phy->tfc = 1;
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}
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phy->link = 1;
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return 0;
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}
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@ -1,143 +0,0 @@
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typedef struct Mii Mii;
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typedef struct MiiPhy MiiPhy;
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enum { /* registers */
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Bmcr = 0, /* Basic Mode Control */
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Bmsr = 1, /* Basic Mode Status */
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Phyidr1 = 2, /* PHY Identifier #1 */
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Phyidr2 = 3, /* PHY Identifier #2 */
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Anar = 4, /* Auto-Negotiation Advertisement */
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Anlpar = 5, /* AN Link Partner Ability */
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Aner = 6, /* AN Expansion */
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Annptr = 7, /* AN Next Page TX */
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Annprr = 8, /* AN Next Page RX */
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Mscr = 9, /* Gb Control */
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Mssr = 10, /* Gb Status */
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Esr = 15, /* Extended Status */
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/* 88e1116-specific paged registers */
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Scr = 16, /* special control register */
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Ssr = 17, /* special status register */
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Ier = 18, /* interrupt enable reg */
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Isr = 19, /* interrupt status reg */
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Escr = 20, /* extended special control reg */
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Recr = 21, /* RX error counter reg */
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Eadr = 22, /* extended address reg (page select) */
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Globsts = 23, /* global status */
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Impover = 24, /* RGMII output impedance override (page 2) */
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Imptarg = 25, /* RGMII output impedance target (page 2) */
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Scr2 = 26, /* special control register 2 */
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NMiiPhyr = 32,
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NMiiPhy = 32,
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};
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enum { /* Bmcr */
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BmcrSs1 = 0x0040, /* Speed Select[1] */
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BmcrCte = 0x0080, /* Collision Test Enable */
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BmcrDm = 0x0100, /* Duplex Mode */
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BmcrRan = 0x0200, /* Restart Auto-Negotiation */
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BmcrI = 0x0400, /* Isolate */
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BmcrPd = 0x0800, /* Power Down */
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BmcrAne = 0x1000, /* Auto-Negotiation Enable */
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BmcrSs0 = 0x2000, /* Speed Select[0] */
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BmcrLe = 0x4000, /* Loopback Enable */
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BmcrR = 0x8000, /* Reset */
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};
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enum { /* Bmsr */
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BmsrEc = 0x0001, /* Extended Capability */
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BmsrJd = 0x0002, /* Jabber Detect */
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BmsrLs = 0x0004, /* Link Status */
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BmsrAna = 0x0008, /* Auto-Negotiation Ability */
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BmsrRf = 0x0010, /* Remote Fault */
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BmsrAnc = 0x0020, /* Auto-Negotiation Complete */
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BmsrPs = 0x0040, /* Preamble Suppression Capable */
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BmsrEs = 0x0100, /* Extended Status */
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Bmsr100T2HD = 0x0200, /* 100BASE-T2 HD Capable */
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Bmsr100T2FD = 0x0400, /* 100BASE-T2 FD Capable */
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Bmsr10THD = 0x0800, /* 10BASE-T HD Capable */
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Bmsr10TFD = 0x1000, /* 10BASE-T FD Capable */
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Bmsr100TXHD = 0x2000, /* 100BASE-TX HD Capable */
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Bmsr100TXFD = 0x4000, /* 100BASE-TX FD Capable */
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Bmsr100T4 = 0x8000, /* 100BASE-T4 Capable */
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};
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enum { /* Anar/Anlpar */
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Ana10HD = 0x0020, /* Advertise 10BASE-T */
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Ana10FD = 0x0040, /* Advertise 10BASE-T FD */
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AnaTXHD = 0x0080, /* Advertise 100BASE-TX */
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AnaTXFD = 0x0100, /* Advertise 100BASE-TX FD */
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AnaT4 = 0x0200, /* Advertise 100BASE-T4 */
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AnaP = 0x0400, /* Pause */
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AnaAP = 0x0800, /* Asymmetrical Pause */
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AnaRf = 0x2000, /* Remote Fault */
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AnaAck = 0x4000, /* Acknowledge */
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AnaNp = 0x8000, /* Next Page Indication */
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};
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enum { /* Mscr */
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Mscr1000THD = 0x0100, /* Advertise 1000BASE-T HD */
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Mscr1000TFD = 0x0200, /* Advertise 1000BASE-T FD */
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};
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enum { /* Mssr */
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Mssr1000THD = 0x0400, /* Link Partner 1000BASE-T HD able */
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Mssr1000TFD = 0x0800, /* Link Partner 1000BASE-T FD able */
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};
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enum { /* Esr */
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Esr1000THD = 0x1000, /* 1000BASE-T HD Capable */
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Esr1000TFD = 0x2000, /* 1000BASE-T FD Capable */
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Esr1000XHD = 0x4000, /* 1000BASE-X HD Capable */
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Esr1000XFD = 0x8000, /* 1000BASE-X FD Capable */
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};
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enum { /* Scr page 0 */
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Pwrdown = 0x0004, /* power down */
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Mdix = 0x0060, /* MDI crossover mode */
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Endetect = 0x0300, /* energy detect */
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};
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enum { /* Scr page 2 */
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Rgmiipwrup = 0x0008, /* RGMII power up: must sw reset after */
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};
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enum { /* Recr page 2 */
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Txtiming = 1<<4,
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Rxtiming = 1<<5,
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};
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typedef struct Mii {
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Lock;
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int nphy;
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int mask;
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MiiPhy* phy[NMiiPhy];
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MiiPhy* curphy;
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void* ctlr;
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int (*mir)(Mii*, int, int);
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int (*miw)(Mii*, int, int, int);
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} Mii;
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typedef struct MiiPhy {
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Mii* mii;
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int oui;
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int phyno;
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int anar;
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int fc;
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int mscr;
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int link;
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int speed;
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int fd;
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int rfc;
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int tfc;
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};
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extern int mii(Mii*, int);
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extern int miiane(Mii*, int, int, int);
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extern int miimir(Mii*, int);
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extern int miimiw(Mii*, int, int);
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extern int miireset(Mii*);
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extern int miistatus(Mii*);
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@ -122,7 +122,7 @@ arch.$O clock.$O fpiarm.$O main.$O mmu.$O screen.$O sdscsi.$O syscall.$O \
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trap.$O: /$objtype/include/ureg.h
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arch.$O syscall.$O main.$O: /sys/include/tos.h
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archkw.$O devether.$O ether1116.$O ethermii.$O: \
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ethermii.h ../port/etherif.h ../port/netif.h
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../port/ethermii.h ../port/etherif.h ../port/netif.h
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archkw.$O devflash.$O flashkw.$O: ../port/flashif.h
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fpi.$O fpiarm.$O fpimem.$O: fpi.h
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l.$O lexception.$O lproc.$O mmu.$O rebootcode.$O: arm.s arm.h mem.h
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