etherimx: fix link negotiation
mdio interrupt command completion handling was broken, as the interrupt handler would clear the mii status register before mdiodone() sees it. handle errors in miistatus() and miiane(), to not get confused.
This commit is contained in:
cinap_lenrek
parent
990ceeef3b
commit
f0fc84aba3
2 changed files with 51 additions and 19 deletions
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@ -9,7 +9,10 @@
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#include "../port/ethermii.h"
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enum {
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Moduleclk = 125000000, /* 125Mhz */
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Ptpclk = 100*Mhz,
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Busclk = 266*Mhz,
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Txclk = 125*Mhz,
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Maxtu = 1518,
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R_BUF_SIZE = ((Maxtu+BLOCKALIGN-1)&~BLOCKALIGN),
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@ -231,6 +234,7 @@ struct Ctlr
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struct {
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Mii;
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int done;
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Rendez;
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} mii[1];
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@ -245,7 +249,7 @@ static int
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mdiodone(void *arg)
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{
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Ctlr *ctlr = arg;
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return rr(ctlr, ENET_EIR) & INT_MII;
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return ctlr->mii->done || (rr(ctlr, ENET_EIR) & INT_MII) != 0;
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}
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static int
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mdiowait(Ctlr *ctlr)
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@ -265,9 +269,13 @@ mdiow(Mii* mii, int phy, int addr, int data)
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Ctlr *ctlr = mii->ctlr;
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data &= 0xFFFF;
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wr(ctlr, ENET_EIR, INT_MII);
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ctlr->mii->done = 0;
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wr(ctlr, ENET_MMFR, MMFR_WR | MMFR_ST | MMFR_TA | phy<<MMFR_PA_SHIFT | addr<<MMFR_RA_SHIFT | data);
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if(mdiowait(ctlr) < 0) return -1;
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if(mdiowait(ctlr) < 0)
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return -1;
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return data;
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}
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static int
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@ -276,8 +284,11 @@ mdior(Mii* mii, int phy, int addr)
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Ctlr *ctlr = mii->ctlr;
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wr(ctlr, ENET_EIR, INT_MII);
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ctlr->mii->done = 0;
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wr(ctlr, ENET_MMFR, MMFR_RD | MMFR_ST | MMFR_TA | phy<<MMFR_PA_SHIFT | addr<<MMFR_RA_SHIFT);
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if(mdiowait(ctlr) < 0) return -1;
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if(mdiowait(ctlr) < 0)
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return -1;
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return rr(ctlr, ENET_MMFR) & 0xFFFF;
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}
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@ -289,11 +300,13 @@ interrupt(Ureg*, void *arg)
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u32int e;
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e = rr(ctlr, ENET_EIR);
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wr(ctlr, ENET_EIR, e);
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if(e & INT_RXF) wakeup(ctlr->rx);
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if(e & INT_TXF) wakeup(ctlr->tx);
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if(e & INT_MII) wakeup(ctlr->mii);
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if(e & INT_MII) {
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ctlr->mii->done = 1;
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wakeup(ctlr->mii);
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}
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wr(ctlr, ENET_EIR, e);
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}
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static void
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@ -450,13 +463,11 @@ linkproc(void *arg)
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Ether *edev = arg;
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Ctlr *ctlr = edev->ctlr;
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MiiPhy *phy;
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int link = -1;
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int link = 0;
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while(waserror())
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;
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miiane(ctlr->mii, ~0, AnaAP|AnaP, ~0);
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miiane(ctlr->mii, ~0, ~0, ~0);
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for(;;){
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miistatus(ctlr->mii);
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phy = ctlr->mii->curphy;
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@ -505,7 +516,7 @@ linkproc(void *arg)
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edev->mbps = phy->speed;
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wr(ctlr, ENET_RDAR, RDAR_ACTIVE);
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}
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}
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edev->link = link;
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print("#l%d: link %d speed %d\n", edev->ctlrno, edev->link, edev->mbps);
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}
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@ -532,7 +543,7 @@ attach(Ether *edev)
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wr(ctlr, ENET_RCR, RCR_MII_MODE | RCR_RGMII_EN | Maxtu<<RCR_MAX_FL_SHIFT);
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/* set MII clock to 2.5Mhz, 10ns hold time */
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wr(ctlr, ENET_MSCR, ((Moduleclk/(2*2500000))-1)<<MSCR_SPEED_SHIFT | ((Moduleclk/10000000)-1)<<MSCR_HOLD_SHIFT);
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wr(ctlr, ENET_MSCR, ((Busclk/(2*2500000))-1)<<MSCR_SPEED_SHIFT | ((Busclk/1000000)-1)<<MSCR_HOLD_SHIFT);
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ctlr->intmask |= INT_MII;
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wr(ctlr, ENET_EIMR, ctlr->intmask);
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@ -586,8 +597,8 @@ attach(Ether *edev)
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wr(ctlr, ENET_TFWR, TFWR_STRFWD);
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/* interrupt coalescing: 200 pkts, 1000 µs */
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wr(ctlr, ENET_RXIC0, IC_EN | 200<<IC_FT_SHIFT | ((1000*Moduleclk)/64000000)<<IC_TT_SHIFT);
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wr(ctlr, ENET_TXIC0, IC_EN | 200<<IC_FT_SHIFT | ((1000*Moduleclk)/64000000)<<IC_TT_SHIFT);
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wr(ctlr, ENET_RXIC0, IC_EN | 200<<IC_FT_SHIFT | ((1000*Txclk)/64000000)<<IC_TT_SHIFT);
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wr(ctlr, ENET_TXIC0, IC_EN | 200<<IC_FT_SHIFT | ((1000*Txclk)/64000000)<<IC_TT_SHIFT);
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ctlr->intmask |= INT_TXF | INT_RXF;
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wr(ctlr, ENET_EIMR, ctlr->intmask);
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@ -708,9 +719,9 @@ pnp(Ether *edev)
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setclkgate("enet1.ipp_ind_mac0_txclk", 0);
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setclkgate("sim_enet.mainclk", 0);
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setclkrate("enet1.ipg_clk", "system_pll1_div3", 266*Mhz);
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setclkrate("enet1.ipp_ind_mac0_txclk", "system_pll2_div8", Moduleclk);
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setclkrate("enet1.ipg_clk_time", "system_pll2_div10", 25*Mhz);
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setclkrate("enet1.ipg_clk", "system_pll1_div3", Busclk);
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setclkrate("enet1.ipp_ind_mac0_txclk", "system_pll2_div8", Txclk);
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setclkrate("enet1.ipg_clk_time", "system_pll2_div10", Ptpclk);
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setclkgate("enet1.ipp_ind_mac0_txclk", 1);
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setclkgate("sim_enet.mainclk", 1);
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@ -87,6 +87,8 @@ miireset(Mii* mii)
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if(mii == nil || mii->ctlr == nil || mii->curphy == nil)
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return -1;
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bmcr = mii->mir(mii, mii->curphy->phyno, Bmcr);
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if(bmcr == -1)
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return -1;
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bmcr |= BmcrR;
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mii->miw(mii, mii->curphy->phyno, Bmcr, bmcr);
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microdelay(1);
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@ -104,6 +106,8 @@ miiane(Mii* mii, int a, int p, int e)
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phyno = mii->curphy->phyno;
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bmsr = mii->mir(mii, phyno, Bmsr);
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if(bmsr == -1)
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return -1;
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if(!(bmsr & BmsrAna))
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return -1;
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@ -113,6 +117,8 @@ miiane(Mii* mii, int a, int p, int e)
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anar = mii->curphy->anar;
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else{
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anar = mii->mir(mii, phyno, Anar);
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if(anar == -1)
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return -1;
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anar &= ~(AnaAP|AnaP|AnaT4|AnaTXFD|AnaTXHD|Ana10FD|Ana10HD);
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if(bmsr & Bmsr10THD)
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anar |= Ana10HD;
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@ -133,6 +139,8 @@ miiane(Mii* mii, int a, int p, int e)
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if(bmsr & BmsrEs){
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mscr = mii->mir(mii, phyno, Mscr);
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if(mscr == -1)
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return -1;
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mscr &= ~(Mscr1000TFD|Mscr1000THD);
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if(e != ~0)
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mscr |= (Mscr1000TFD|Mscr1000THD) & e;
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@ -140,6 +148,8 @@ miiane(Mii* mii, int a, int p, int e)
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mscr = mii->curphy->mscr;
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else{
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r = mii->mir(mii, phyno, Esr);
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if(r == -1)
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return -1;
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if(r & Esr1000THD)
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mscr |= Mscr1000THD;
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if(r & Esr1000TFD)
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@ -148,9 +158,12 @@ miiane(Mii* mii, int a, int p, int e)
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mii->curphy->mscr = mscr;
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mii->miw(mii, phyno, Mscr, mscr);
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}
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mii->miw(mii, phyno, Anar, anar);
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if(mii->miw(mii, phyno, Anar, anar) == -1)
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return -1;
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r = mii->mir(mii, phyno, Bmcr);
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if(r == -1)
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return -1;
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if(!(r & BmcrR)){
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r |= BmcrAne|BmcrRan;
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mii->miw(mii, phyno, Bmcr, r);
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@ -175,12 +188,16 @@ miistatus(Mii* mii)
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* (Read status twice as the Ls bit is sticky).
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*/
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bmsr = mii->mir(mii, phyno, Bmsr);
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if(bmsr == -1)
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return -1;
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if(!(bmsr & (BmsrAnc|BmsrAna))) {
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// print("miistatus: auto-neg incomplete\n");
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return -1;
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}
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bmsr = mii->mir(mii, phyno, Bmsr);
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if(bmsr == -1)
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return -1;
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if(!(bmsr & BmsrLs)){
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// print("miistatus: link down\n");
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phy->link = 0;
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@ -190,6 +207,8 @@ miistatus(Mii* mii)
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phy->speed = phy->fd = phy->rfc = phy->tfc = 0;
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if(phy->mscr){
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r = mii->mir(mii, phyno, Mssr);
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if(r == -1)
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return -1;
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if((phy->mscr & Mscr1000TFD) && (r & Mssr1000TFD)){
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phy->speed = 1000;
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phy->fd = 1;
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@ -199,6 +218,8 @@ miistatus(Mii* mii)
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}
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anlpar = mii->mir(mii, phyno, Anlpar);
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if(anlpar == -1)
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return -1;
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if(phy->speed == 0){
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r = phy->anar & anlpar;
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if(r & AnaTXFD){
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