added BCM57xx driver
This commit is contained in:
aiju
parent
ced69dcde4
commit
e0b36c7084
2 changed files with 670 additions and 0 deletions
669
sys/src/9/pc/etherbcm.c
Normal file
669
sys/src/9/pc/etherbcm.c
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@ -0,0 +1,669 @@
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/*
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* Broadcom BCM57xx
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* Not implemented:
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* proper fatal error handling
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* multiple rings
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* QoS
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* checksum offloading
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
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typedef struct Ctlr Ctlr;
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struct Ctlr {
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Lock txlock;
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Ctlr *link;
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Pcidev *pdev;
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ulong *nic, *status;
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/* One Ring to find them, One Ring to bring them all and in the darkness bind them */
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ulong *recvret, *recvprod, *sendr;
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ulong port;
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ulong recvreti, recvprodi, sendri, sendcleani;
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Block **sends;
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int active, duplex;
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};
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enum {
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RecvRetRingLen = 0x200,
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RecvProdRingLen = 0x200,
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SendRingLen = 0x200,
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};
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enum {
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Reset = 1<<0,
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Enable = 1<<1,
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Attn = 1<<2,
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PowerControlStatus = 0x4C,
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MiscHostCtl = 0x68,
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ClearIntA = 1<<0,
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MaskPCIInt = 1<<1,
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IndirectAccessEnable = 1<<7,
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EnablePCIStateRegister = 1<<4,
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EnableClockControlRegister = 1<<5,
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TaggedStatus = 1<<9,
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DMARWControl = 0x6C,
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DMAWatermarkMask = ~(7<<19),
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DMAWatermarkValue = 3<<19,
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MemoryWindow = 0x7C,
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MemoryWindowData = 0x84,
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SendRCB = 0x100,
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RecvRetRCB = 0x200,
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InterruptMailbox = 0x204,
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RecvProdBDRingIndex = 0x26c,
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RecvBDRetRingIndex = 0x284,
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SendBDRingHostIndex = 0x304,
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MACMode = 0x400,
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MACPortMask = ~((1<<3)|(1<<2)),
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MACPortGMII = 1<<3,
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MACPortMII = 1<<2,
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MACEnable = (1<<23) | (1<<22) | (1<<21) | (1 << 15) | (1 << 14) | (1<<12) | (1<<11),
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MACHalfDuplex = 1<<1,
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MACEventStatus = 0x404,
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MACEventEnable = 0x408,
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MACAddress = 0x410,
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EthernetRandomBackoff = 0x438,
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ReceiveMTU = 0x43C,
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MIComm = 0x44C,
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MIStatus = 0x450,
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MIMode = 0x454,
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ReceiveMACMode = 0x468,
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TransmitMACMode = 0x45C,
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TransmitMACLengths = 0x464,
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MACHash = 0x470,
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ReceiveRules = 0x480,
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ReceiveRulesConfiguration = 0x500,
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LowWatermarkMaximum = 0x504,
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LowWatermarkMaxMask = ~0xFFFF,
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LowWatermarkMaxValue = 2,
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SendDataInitiatorMode = 0xC00,
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SendInitiatorConfiguration = 0x0C08,
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SendStats = 1<<0,
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SendInitiatorMask = 0x0C0C,
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SendDataCompletionMode = 0x1000,
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SendBDSelectorMode = 0x1400,
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SendBDInitiatorMode = 0x1800,
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SendBDCompletionMode = 0x1C00,
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ReceiveListPlacementMode = 0x2000,
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ReceiveListPlacement = 0x2010,
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ReceiveListPlacementConfiguration = 0x2014,
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ReceiveStats = 1<<0,
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ReceiveListPlacementMask = 0x2018,
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ReceiveDataBDInitiatorMode = 0x2400,
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ReceiveBDHostAddr = 0x2450,
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ReceiveBDFlags = 0x2458,
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ReceiveBDNIC = 0x245C,
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ReceiveDataCompletionMode = 0x2800,
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ReceiveBDInitiatorMode = 0x2C00,
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ReceiveBDRepl = 0x2C18,
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ReceiveBDCompletionMode = 0x3000,
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HostCoalescingMode = 0x3C00,
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HostCoalescingRecvTicks = 0x3C08,
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HostCoalescingSendTicks = 0x3C0C,
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RecvMaxCoalescedFrames = 0x3C10,
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SendMaxCoalescedFrames = 0x3C14,
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RecvMaxCoalescedFramesInt = 0x3C20,
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SendMaxCoalescedFramesInt = 0x3C24,
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StatusBlockHostAddr = 0x3C38,
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FlowAttention = 0x3C48,
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MemArbiterMode = 0x4000,
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BufferManMode = 0x4400,
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MBUFLowWatermark = 0x4414,
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MBUFHighWatermark = 0x4418,
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ReadDMAMode = 0x4800,
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ReadDMAStatus = 0x4804,
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WriteDMAMode = 0x4C00,
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WriteDMAStatus = 0x4C04,
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RISCState = 0x5004,
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FTQReset = 0x5C00,
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MSIMode = 0x6000,
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ModeControl = 0x6800,
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ByteWordSwap = (1<<4)|(1<<5)|(1<<2),//|(1<<1),
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HostStackUp = 1<<16,
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HostSendBDs = 1<<17,
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InterruptOnMAC = 1<<26,
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MiscConfiguration = 0x6804,
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CoreClockBlocksReset = 1<<0,
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GPHYPowerDownOverride = 1<<26,
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DisableGRCResetOnPCIE = 1<<29,
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TimerMask = ~0xFF,
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TimerValue = 65<<1,
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MiscLocalControl = 0x6808,
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InterruptOnAttn = 1<<3,
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AutoSEEPROM = 1<<24,
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SwArbitration = 0x7020,
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SwArbitSet1 = 1<<1,
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SwArbitWon1 = 1<<9,
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TLPControl = 0x7C00,
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PhyControl = 0x00,
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PhyStatus = 0x01,
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PhyLinkStatus = 1<<2,
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PhyAutoNegComplete = 1<<5,
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PhyPartnerStatus = 0x05,
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Phy100FD = 1<<8,
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Phy100HD = 1<<7,
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Phy10FD = 1<<6,
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Phy10HD = 1<<5,
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PhyGbitStatus = 0x0A,
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Phy1000FD = 1<<12,
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Phy1000HD = 1<<11,
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PhyAuxControl = 0x18,
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PhyIntStatus = 0x1A,
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PhyIntMask = 0x1B,
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Updated = 1<<0,
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LinkStateChange = 1<<1,
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Error = 1<<2,
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PacketEnd = 1<<2,
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FrameError = 1<<10,
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};
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#define csr32(c, r) ((c)->nic[(r)/4])
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#define mem32(c, r) csr32(c, (r)+0x8000)
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static Ctlr *bcmhead, *bcmtail;
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static ulong
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dummyread(ulong x)
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{
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return x;
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}
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static int
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miir(Ctlr *ctlr, int ra)
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{
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while(csr32(ctlr, MIComm) & (1<<29));
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csr32(ctlr, MIComm) = (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
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while(csr32(ctlr, MIComm) & (1<<29));
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if(csr32(ctlr, MIComm) & (1<<28)) return -1;
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return csr32(ctlr, MIComm) & 0xFFFF;
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}
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static int
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miiw(Ctlr *ctlr, int ra, int value)
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{
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while(csr32(ctlr, MIComm) & (1<<29));
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csr32(ctlr, MIComm) = (value & 0xFFFF) | (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
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while(csr32(ctlr, MIComm) & (1<<29));
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return 0;
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}
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static void
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checklink(Ether *edev)
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{
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Ctlr *ctlr;
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ulong i;
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ctlr = edev->ctlr;
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miir(ctlr, PhyStatus); /* dummy read necessary */
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if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
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edev->link = 0;
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edev->mbps = 1000;
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ctlr->duplex = 1;
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print("bcm: no link\n");
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goto out;
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}
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edev->link = 1;
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while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
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i = miir(ctlr, PhyGbitStatus);
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if(i & (Phy1000FD | Phy1000HD)) {
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edev->mbps = 1000;
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ctlr->duplex = (i & Phy1000FD) != 0;
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} else if(i = miir(ctlr, PhyPartnerStatus), i & (Phy100FD | Phy100HD)) {
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edev->mbps = 100;
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ctlr->duplex = (i & Phy100FD) != 0;
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} else if(i & (Phy10FD | Phy10HD)) {
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edev->mbps = 10;
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ctlr->duplex = (i & Phy10FD) != 0;
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} else {
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edev->link = 0;
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edev->mbps = 1000;
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ctlr->duplex = 1;
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print("bcm: link partner supports neither 10/100/1000 Mbps\n");
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goto out;
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}
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print("bcm: %d Mbps link, %s duplex\n", edev->mbps, ctlr->duplex ? "full" : "half");
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out:
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if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
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else csr32(ctlr, MACMode) |= MACHalfDuplex;
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if(edev->mbps >= 1000)
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csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
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else
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csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortMII;
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csr32(ctlr, MACEventStatus) |= (1<<4) | (1<<3); /* undocumented bits (sync and config changed) */
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}
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static ulong*
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currentrecvret(Ctlr *ctlr)
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{
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if(ctlr->recvreti == (ctlr->status[4] & 0xFFFF)) return 0;
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return ctlr->recvret + ctlr->recvreti * 8;
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}
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static void
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consumerecvret(Ctlr *ctlr)
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{
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csr32(ctlr, RecvBDRetRingIndex) = ctlr->recvreti = (ctlr->recvreti + 1) & (RecvRetRingLen - 1);
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}
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static int
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replenish(Ctlr *ctlr)
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{
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ulong *next;
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ulong incr;
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Block *bp;
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incr = (ctlr->recvprodi + 1) & (RecvProdRingLen - 1);
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if(incr == (ctlr->status[2] >> 16)) return -1;
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bp = iallocb(Rbsz);
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if(bp == nil) {
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print("bcm: out of memory for receive buffers\n");
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return -1;
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}
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next = ctlr->recvprod + ctlr->recvprodi * 8;
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memset(next, 0, 32);
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next[1] = PADDR(bp->rp);
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next[2] = Rbsz;
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next[7] = (ulong) bp;
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csr32(ctlr, RecvProdBDRingIndex) = ctlr->recvprodi = incr;
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return 0;
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}
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static void
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bcmreceive(Ether *edev)
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{
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Ctlr *ctlr;
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Block *bp;
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ulong *pkt, len;
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ctlr = edev->ctlr;
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for(; pkt = currentrecvret(ctlr); replenish(ctlr), consumerecvret(ctlr)) {
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bp = (Block*) pkt[7];
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len = pkt[2] & 0xFFFF;
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bp->wp = bp->rp + len;
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if((pkt[3] & PacketEnd) == 0) print("bcm: partial frame received -- shouldn't happen\n");
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if(pkt[3] & FrameError) {
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freeb(bp); /* dump erroneous packets */
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} else {
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etheriq(edev, bp, 1);
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}
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}
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}
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static void
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bcmtransclean(Ether *edev)
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{
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Ctlr *ctlr;
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ulong incr;
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ctlr = edev->ctlr;
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ilock(&ctlr->txlock);
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while(ctlr->sendcleani != (ctlr->status[4] >> 16)) {
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freeb(ctlr->sends[ctlr->sendri]);
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ctlr->sends[ctlr->sendri] = 0;
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ctlr->sendcleani = (ctlr->sendcleani + 1) & (SendRingLen - 1);
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}
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iunlock(&ctlr->txlock);
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}
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static void
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bcmtransmit(Ether *edev)
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{
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Ctlr *ctlr;
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Block *bp;
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ulong *next;
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ulong incr;
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ctlr = edev->ctlr;
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ilock(&ctlr->txlock);
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while(1) {
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incr = (ctlr->sendri + 1) & (SendRingLen - 1);
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if(incr == (ctlr->status[4] >> 16)) {
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print("bcm: send queue full\n");
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break;
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}
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bp = qget(edev->oq);
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if(bp == nil) break;
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next = ctlr->sendr + ctlr->sendri * 4;
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next[0] = 0;
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next[1] = PADDR(bp->rp);
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next[2] = (BLEN(bp) << 16) | PacketEnd;
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next[3] = 0;
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ctlr->sends[ctlr->sendri] = bp;
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csr32(ctlr, SendBDRingHostIndex) = ctlr->sendri = incr;
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}
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iunlock(&ctlr->txlock);
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}
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static void
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bcmerror(Ether *edev)
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{
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Ctlr *ctlr;
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ctlr = edev->ctlr;
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if(csr32(ctlr, FlowAttention)) {
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||||||
|
if(csr32(ctlr, FlowAttention) & 0xF8FF8080UL) {
|
||||||
|
panic("bcm: fatal error %#.8ux", csr32(ctlr, FlowAttention));
|
||||||
|
}
|
||||||
|
csr32(ctlr, FlowAttention) = 0;
|
||||||
|
}
|
||||||
|
csr32(ctlr, MACEventStatus) = 0; /* worth ignoring */
|
||||||
|
if(csr32(ctlr, ReadDMAStatus) || csr32(ctlr, WriteDMAStatus)) {
|
||||||
|
print("bcm: DMA error\n");
|
||||||
|
csr32(ctlr, ReadDMAStatus) = 0;
|
||||||
|
csr32(ctlr, WriteDMAStatus) = 0;
|
||||||
|
}
|
||||||
|
if(csr32(ctlr, RISCState)) {
|
||||||
|
if(csr32(ctlr, RISCState) & 0x78000403) {
|
||||||
|
panic("bcm: RISC halted %#.8ux", csr32(ctlr, RISCState));
|
||||||
|
}
|
||||||
|
csr32(ctlr, RISCState) = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
bcminterrupt(Ureg*, void *arg)
|
||||||
|
{
|
||||||
|
Ether *edev;
|
||||||
|
Ctlr *ctlr;
|
||||||
|
ulong status, tag;
|
||||||
|
|
||||||
|
edev = arg;
|
||||||
|
ctlr = edev->ctlr;
|
||||||
|
dummyread(csr32(ctlr, InterruptMailbox));
|
||||||
|
csr32(ctlr, InterruptMailbox) = 1;
|
||||||
|
status = ctlr->status[0];
|
||||||
|
tag = ctlr->status[1];
|
||||||
|
ctlr->status[0] = 0;
|
||||||
|
if(status & Error) bcmerror(edev);
|
||||||
|
if(status & LinkStateChange) checklink(edev);
|
||||||
|
// print("bcm: interrupt %8ulx %8ulx\n", ctlr->status[2], ctlr->status[4]);
|
||||||
|
bcmreceive(edev);
|
||||||
|
bcmtransclean(edev);
|
||||||
|
bcmtransmit(edev);
|
||||||
|
csr32(ctlr, InterruptMailbox) = tag << 24;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
bcminit(Ether *edev)
|
||||||
|
{
|
||||||
|
ulong i, j;
|
||||||
|
Ctlr *ctlr;
|
||||||
|
|
||||||
|
ctlr = edev->ctlr;
|
||||||
|
print("bcm: reset\n");
|
||||||
|
/* initialization procedure according to the datasheet */
|
||||||
|
csr32(ctlr, MiscHostCtl) |= MaskPCIInt | ClearIntA;
|
||||||
|
csr32(ctlr, SwArbitration) |= SwArbitSet1;
|
||||||
|
while((csr32(ctlr, SwArbitration) & SwArbitWon1) == 0);
|
||||||
|
csr32(ctlr, MemArbiterMode) |= Enable;
|
||||||
|
csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister;
|
||||||
|
csr32(ctlr, MemoryWindow) = 0;
|
||||||
|
mem32(ctlr, 0xB50) = 0x4B657654; /* magic number bullshit */
|
||||||
|
csr32(ctlr, MiscConfiguration) |= GPHYPowerDownOverride | DisableGRCResetOnPCIE;
|
||||||
|
csr32(ctlr, MiscConfiguration) |= CoreClockBlocksReset;
|
||||||
|
microdelay(100000);
|
||||||
|
ctlr->pdev->pcr |= 1<<1;
|
||||||
|
pcisetbme(ctlr->pdev);
|
||||||
|
csr32(ctlr, MiscHostCtl) |= MaskPCIInt;
|
||||||
|
csr32(ctlr, MemArbiterMode) |= Enable;
|
||||||
|
csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister | TaggedStatus;
|
||||||
|
csr32(ctlr, ModeControl) |= ByteWordSwap;
|
||||||
|
csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
|
||||||
|
microdelay(40000);
|
||||||
|
while(mem32(ctlr, 0xB50) != 0xB49A89AB);
|
||||||
|
csr32(ctlr, TLPControl) |= (1<<25) | (1<<29);
|
||||||
|
memset(ctlr->status, 0, 20);
|
||||||
|
csr32(ctlr, DMARWControl) = (csr32(ctlr, DMARWControl) & DMAWatermarkMask) | DMAWatermarkValue;
|
||||||
|
csr32(ctlr, ModeControl) |= HostSendBDs | HostStackUp | InterruptOnMAC;
|
||||||
|
csr32(ctlr, MiscConfiguration) = (csr32(ctlr, MiscConfiguration) & TimerMask) | TimerValue;
|
||||||
|
csr32(ctlr, MBUFLowWatermark) = 0x20;
|
||||||
|
csr32(ctlr, MBUFHighWatermark) = 0x60;
|
||||||
|
csr32(ctlr, LowWatermarkMaximum) = (csr32(ctlr, LowWatermarkMaximum) & LowWatermarkMaxMask) | LowWatermarkMaxValue;
|
||||||
|
csr32(ctlr, BufferManMode) |= Enable | Attn;
|
||||||
|
while((csr32(ctlr, BufferManMode) & Enable) == 0);
|
||||||
|
csr32(ctlr, FTQReset) = -1;
|
||||||
|
csr32(ctlr, FTQReset) = 0;
|
||||||
|
while(csr32(ctlr, FTQReset));
|
||||||
|
csr32(ctlr, ReceiveBDHostAddr) = 0;
|
||||||
|
csr32(ctlr, ReceiveBDHostAddr + 4) = PADDR(ctlr->recvprod);
|
||||||
|
csr32(ctlr, ReceiveBDFlags) = RecvProdRingLen << 16;
|
||||||
|
csr32(ctlr, ReceiveBDNIC) = 0x6000;
|
||||||
|
csr32(ctlr, ReceiveBDRepl) = 25;
|
||||||
|
csr32(ctlr, SendBDRingHostIndex) = 0;
|
||||||
|
csr32(ctlr, SendBDRingHostIndex+4) = 0;
|
||||||
|
mem32(ctlr, SendRCB) = 0;
|
||||||
|
mem32(ctlr, SendRCB + 4) = PADDR(ctlr->sendr);
|
||||||
|
mem32(ctlr, SendRCB + 8) = SendRingLen << 16;
|
||||||
|
mem32(ctlr, SendRCB + 12) = 0x4000;
|
||||||
|
for(i=1;i<4;i++)
|
||||||
|
mem32(ctlr, RecvRetRCB + i * 0x10 + 8) = 2;
|
||||||
|
mem32(ctlr, RecvRetRCB) = 0;
|
||||||
|
mem32(ctlr, RecvRetRCB + 4) = PADDR(ctlr->recvret);
|
||||||
|
mem32(ctlr, RecvRetRCB + 8) = RecvRetRingLen << 16;
|
||||||
|
csr32(ctlr, RecvProdBDRingIndex) = 0;
|
||||||
|
csr32(ctlr, RecvProdBDRingIndex+4) = 0;
|
||||||
|
/* this delay is not in the datasheet, but necessary; Broadcom is fucking with us */
|
||||||
|
microdelay(1000);
|
||||||
|
i = csr32(ctlr, 0x410);
|
||||||
|
j = edev->ea[0] = i >> 8;
|
||||||
|
j += edev->ea[1] = i;
|
||||||
|
i = csr32(ctlr, MACAddress + 4);
|
||||||
|
j += edev->ea[2] = i >> 24;
|
||||||
|
j += edev->ea[3] = i >> 16;
|
||||||
|
j += edev->ea[4] = i >> 8;
|
||||||
|
j += edev->ea[5] = i;
|
||||||
|
csr32(ctlr, EthernetRandomBackoff) = j & 0x3FF;
|
||||||
|
csr32(ctlr, ReceiveMTU) = Rbsz;
|
||||||
|
csr32(ctlr, TransmitMACLengths) = 0x2620;
|
||||||
|
csr32(ctlr, ReceiveListPlacement) = 1<<3; /* one list */
|
||||||
|
csr32(ctlr, ReceiveListPlacementMask) = 0xFFFFFF;
|
||||||
|
csr32(ctlr, ReceiveListPlacementConfiguration) |= ReceiveStats;
|
||||||
|
csr32(ctlr, SendInitiatorMask) = 0xFFFFFF;
|
||||||
|
csr32(ctlr, SendInitiatorConfiguration) |= SendStats;
|
||||||
|
csr32(ctlr, HostCoalescingMode) = 0;
|
||||||
|
while(csr32(ctlr, HostCoalescingMode) != 0);
|
||||||
|
csr32(ctlr, HostCoalescingRecvTicks) = 150;
|
||||||
|
csr32(ctlr, HostCoalescingSendTicks) = 150;
|
||||||
|
csr32(ctlr, RecvMaxCoalescedFrames) = 10;
|
||||||
|
csr32(ctlr, SendMaxCoalescedFrames) = 10;
|
||||||
|
csr32(ctlr, RecvMaxCoalescedFramesInt) = 0;
|
||||||
|
csr32(ctlr, SendMaxCoalescedFramesInt) = 0;
|
||||||
|
csr32(ctlr, StatusBlockHostAddr) = 0;
|
||||||
|
csr32(ctlr, StatusBlockHostAddr + 4) = PADDR(ctlr->status);
|
||||||
|
csr32(ctlr, HostCoalescingMode) |= Enable;
|
||||||
|
csr32(ctlr, ReceiveBDCompletionMode) |= Enable | Attn;
|
||||||
|
csr32(ctlr, ReceiveListPlacementMode) |= Enable;
|
||||||
|
csr32(ctlr, MACMode) |= MACEnable;
|
||||||
|
csr32(ctlr, MiscLocalControl) |= InterruptOnAttn | AutoSEEPROM;
|
||||||
|
csr32(ctlr, InterruptMailbox) = 0;
|
||||||
|
csr32(ctlr, WriteDMAMode) |= 0x200003fe; /* pulled out of my nose */
|
||||||
|
csr32(ctlr, ReadDMAMode) |= 0x3fe;
|
||||||
|
csr32(ctlr, ReceiveDataCompletionMode) |= Enable | Attn;
|
||||||
|
csr32(ctlr, SendDataCompletionMode) |= Enable;
|
||||||
|
csr32(ctlr, SendBDCompletionMode) |= Enable | Attn;
|
||||||
|
csr32(ctlr, ReceiveBDInitiatorMode) |= Enable | Attn;
|
||||||
|
csr32(ctlr, ReceiveDataBDInitiatorMode) |= Enable | (1<<4);
|
||||||
|
csr32(ctlr, SendDataInitiatorMode) |= Enable;
|
||||||
|
csr32(ctlr, SendBDInitiatorMode) |= Enable | Attn;
|
||||||
|
csr32(ctlr, SendBDSelectorMode) |= Enable | Attn;
|
||||||
|
ctlr->recvprodi = 0;
|
||||||
|
while(replenish(ctlr) >= 0);
|
||||||
|
csr32(ctlr, TransmitMACMode) |= Enable;
|
||||||
|
csr32(ctlr, ReceiveMACMode) |= Enable;
|
||||||
|
csr32(ctlr, PowerControlStatus) &= ~3;
|
||||||
|
csr32(ctlr, MIStatus) |= 1<<0;
|
||||||
|
csr32(ctlr, MACEventEnable) = 0;
|
||||||
|
csr32(ctlr, MACEventStatus) |= (1<<12);
|
||||||
|
csr32(ctlr, MIMode) = 0xC0000;
|
||||||
|
microdelay(40);
|
||||||
|
miiw(ctlr, PhyControl, 1<<15);
|
||||||
|
while(miir(ctlr, PhyControl) & (1<<15));
|
||||||
|
miiw(ctlr, PhyAuxControl, 2);
|
||||||
|
miir(ctlr, PhyIntStatus);
|
||||||
|
miir(ctlr, PhyIntStatus);
|
||||||
|
miiw(ctlr, PhyIntMask, ~(1<<1));
|
||||||
|
checklink(edev);
|
||||||
|
csr32(ctlr, MACEventEnable) |= 1<<12;
|
||||||
|
csr32(ctlr, MACHash) = -1;
|
||||||
|
csr32(ctlr, MACHash+4) = -1;
|
||||||
|
csr32(ctlr, MACHash+8) = -1;
|
||||||
|
csr32(ctlr, MACHash+12) = -1;
|
||||||
|
for(i = 0; i < 8; i++) csr32(ctlr, ReceiveRules + 8 * i) = 0;
|
||||||
|
csr32(ctlr, ReceiveRulesConfiguration) = 1 << 3;
|
||||||
|
csr32(ctlr, MSIMode) &= ~Enable;
|
||||||
|
while(csr32(ctlr, MSIMode) & Enable);
|
||||||
|
csr32(ctlr, MiscHostCtl) &= ~(MaskPCIInt | ClearIntA);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
bcmpci(void)
|
||||||
|
{
|
||||||
|
Pcidev *pdev;
|
||||||
|
|
||||||
|
pdev = nil;
|
||||||
|
while(pdev = pcimatch(pdev, 0, 0)) {
|
||||||
|
Ctlr *ctlr;
|
||||||
|
void *mem;
|
||||||
|
|
||||||
|
if(pdev->ccrb != 2 || pdev->ccru != 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
switch((pdev->vid<<16) | pdev->did){
|
||||||
|
default: continue;
|
||||||
|
case 0x14e4165a:
|
||||||
|
case 0x14e4167d:
|
||||||
|
case 0x14e41670:
|
||||||
|
case 0x14e41672:
|
||||||
|
case 0x14e41673:
|
||||||
|
case 0x14e41674:
|
||||||
|
case 0x14e4167A:
|
||||||
|
case 0x14e4167b:
|
||||||
|
case 0x14e41693:
|
||||||
|
case 0x14e4169B:
|
||||||
|
case 0x14e41712:
|
||||||
|
case 0x14e41713:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
pcisetbme(pdev);
|
||||||
|
pcisetpms(pdev, 0);
|
||||||
|
ctlr = malloc(sizeof(Ctlr));
|
||||||
|
if(ctlr == nil) {
|
||||||
|
print("bcm: unable to alloc Ctlr\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
|
||||||
|
if(mem == nil) {
|
||||||
|
print("bcm: can't map %8.8luX\n", pdev->mem[0].bar);
|
||||||
|
free(ctlr);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
ctlr->pdev = pdev;
|
||||||
|
ctlr->nic = mem;
|
||||||
|
ctlr->port = pdev->mem[0].bar & ~0x0F;
|
||||||
|
ctlr->status = xspanalloc(20, 16, 0);
|
||||||
|
ctlr->recvprod = xspanalloc(32 * RecvProdRingLen, 16, 0);
|
||||||
|
ctlr->recvret = xspanalloc(32 * RecvRetRingLen, 16, 0);
|
||||||
|
ctlr->sendr = xspanalloc(16 * SendRingLen, 16, 0);
|
||||||
|
ctlr->sends = malloc(sizeof(Block) * SendRingLen);
|
||||||
|
if(bcmhead != nil)
|
||||||
|
bcmtail->link = ctlr;
|
||||||
|
else
|
||||||
|
bcmhead = ctlr;
|
||||||
|
bcmtail = ctlr;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
bcmpromiscuous(void* arg, int on)
|
||||||
|
{
|
||||||
|
Ctlr *ctlr;
|
||||||
|
|
||||||
|
ctlr = ((Ether*)arg)->ctlr;
|
||||||
|
if(on)
|
||||||
|
csr32(ctlr, ReceiveMACMode) |= 1<<8;
|
||||||
|
else
|
||||||
|
csr32(ctlr, ReceiveMACMode) &= ~(1<<8);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
bcmmulticast(void*, uchar*, int)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
bcmpnp(Ether* edev)
|
||||||
|
{
|
||||||
|
Ctlr *ctlr;
|
||||||
|
|
||||||
|
if(bcmhead == nil)
|
||||||
|
bcmpci();
|
||||||
|
|
||||||
|
for(ctlr = bcmhead; ctlr != nil; ctlr = ctlr->link) {
|
||||||
|
if(ctlr->active)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
if(edev->port == 0 || edev->port == ctlr->port) {
|
||||||
|
ctlr->active = 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(ctlr == nil)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
edev->ctlr = ctlr;
|
||||||
|
edev->port = ctlr->port;
|
||||||
|
edev->irq = ctlr->pdev->intl;
|
||||||
|
edev->tbdf = ctlr->pdev->tbdf;
|
||||||
|
edev->interrupt = bcminterrupt;
|
||||||
|
edev->transmit = bcmtransmit;
|
||||||
|
edev->multicast = bcmmulticast;
|
||||||
|
edev->promiscuous = bcmpromiscuous;
|
||||||
|
edev->arg = edev;
|
||||||
|
edev->mbps = 1000;
|
||||||
|
|
||||||
|
bcminit(edev);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
etherbcmlink(void)
|
||||||
|
{
|
||||||
|
addethercard("BCM57xx", bcmpnp);
|
||||||
|
}
|
||||||
|
|
@ -52,6 +52,7 @@ link
|
||||||
ether82563 pci
|
ether82563 pci
|
||||||
ether82557 pci
|
ether82557 pci
|
||||||
ether83815 pci
|
ether83815 pci
|
||||||
|
etherbcm pci
|
||||||
etherdp83820 pci
|
etherdp83820 pci
|
||||||
etherec2t ether8390
|
etherec2t ether8390
|
||||||
etherelnk3 pci
|
etherelnk3 pci
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue