usbxhci: implement recovery from host controller errors
This commit is contained in:
cinap_lenrek
parent
7d1b9e39f7
commit
e0474599dd
1 changed files with 124 additions and 33 deletions
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@ -249,6 +249,7 @@ struct Ctlr
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void (*setrptr)(u32int*, u64int);
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Rendez recover;
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void *active;
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uintptr base;
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};
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@ -271,6 +272,7 @@ struct Epio
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static char Ebadlen[] = "bad usb request length";
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static char Enotconfig[] = "usb endpoint not configured";
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static char Erecover[] = "xhci controller needs reset";
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static void
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setrptr32(u32int *reg, u64int pa)
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@ -406,6 +408,26 @@ shutdown(Hci *hp)
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pciclrbme(ctlr->pcidev);
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}
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static void
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release(Ctlr *ctlr)
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{
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int i;
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freering(ctlr->cr);
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for(i=0; i<nelem(ctlr->er); i++){
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freering(&ctlr->er[i]);
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free(ctlr->erst[i]);
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ctlr->erst[i] = nil;
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}
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free(ctlr->port), ctlr->port = nil;
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free(ctlr->slot), ctlr->slot = nil;
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free(ctlr->dcba), ctlr->dcba = nil;
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free(ctlr->sba), ctlr->sba = nil;
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free(ctlr->sbp), ctlr->sbp = nil;
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}
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static void recover(void *arg);
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static void
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init(Hci *hp)
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{
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@ -437,17 +459,7 @@ init(Hci *hp)
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if(waserror()){
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shutdown(hp);
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freering(ctlr->cr);
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for(i=0; i<nelem(ctlr->er); i++){
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freering(&ctlr->er[i]);
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free(ctlr->erst[i]);
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ctlr->erst[i] = nil;
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}
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free(ctlr->port), ctlr->port = nil;
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free(ctlr->slot), ctlr->slot = nil;
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free(ctlr->dcba), ctlr->dcba = nil;
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free(ctlr->sba), ctlr->sba = nil;
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free(ctlr->sbp), ctlr->sbp = nil;
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release(ctlr);
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nexterror();
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}
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@ -544,6 +556,80 @@ init(Hci *hp)
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ctlr->opr[USBCMD] = RUNSTOP|INTE|HSEE|EWE;
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for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != 0 && i<100; i++)
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tsleep(&up->sleep, return0, nil, 10);
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kproc("xhcirecover", recover, hp);
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}
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static int
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needrecover(void *arg)
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{
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Ctlr *ctlr = arg;
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return ctlr->er->stopped ||
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(ctlr->opr[USBSTS] & (HCH|HCE|HSE)) != 0;
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}
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static void
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recover(void *arg)
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{
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Hci *hp = arg;
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Ctlr *ctlr = hp->aux;
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while(waserror())
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;
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while(!needrecover(ctlr))
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tsleep(&ctlr->recover, needrecover, ctlr, 1000);
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shutdown(hp);
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/*
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* flush all transactions and wait until all devices have
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* been detached by usbd.
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*/
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for(;;){
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int i, j, active;
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ilock(ctlr->cr);
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ctlr->cr->stopped = 1;
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flushring(ctlr->cr);
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iunlock(ctlr->cr);
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active = 0;
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qlock(&ctlr->slotlock);
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for(i=1; i<=ctlr->nslots; i++){
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Slot *slot = ctlr->slot[i];
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if(slot == nil)
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continue;
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active++;
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for(j=0; j < slot->nep; j++){
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Ring *ring = &slot->epr[j];
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if(ring->base == nil)
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continue;
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ilock(ring);
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ring->stopped = 1;
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flushring(ring);
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iunlock(ring);
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}
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}
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qunlock(&ctlr->slotlock);
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if(active == 0)
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break;
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tsleep(&up->sleep, return0, nil, 100);
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}
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qlock(&ctlr->slotlock);
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qlock(&ctlr->cmdlock);
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release(ctlr);
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if(waserror()) {
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print("xhci recovery failed: %s\n", up->errstr);
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} else {
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init(hp);
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poperror();
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}
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qunlock(&ctlr->cmdlock);
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qunlock(&ctlr->slotlock);
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}
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static void
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@ -679,14 +765,11 @@ ctlrcmd(Ctlr *ctlr, u32int c, u32int s, u64int p, u32int *er)
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char *err;
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qlock(&ctlr->cmdlock);
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if((ctlr->opr[USBSTS] & (HCH|HCE|HSE)) != 0){
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if(needrecover(ctlr)){
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qunlock(&ctlr->cmdlock);
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return "xhci busted";
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return Erecover;
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}
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ctlr->cr->stopped = 0;
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queuetd(ctlr->cr, c, s, p, w);
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err = waittd(ctlr, w, 5000);
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@ -779,11 +862,9 @@ interrupt(Ureg*, void *arg)
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case ER_HCE:
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iprint("xhci: host controller error: %ux %ux %ux %ux\n",
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td[0], td[1], td[2], td[3]);
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ilock(ctlr->cr);
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ctlr->cr->stopped = 1;
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flushring(ctlr->cr);
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iunlock(ctlr->cr);
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break;
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ctlr->er->stopped = 1;
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wakeup(&ctlr->recover);
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return;
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case ER_PORTSC:
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break;
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case ER_BWREQ:
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@ -802,17 +883,18 @@ static void
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freeslot(void *arg)
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{
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Slot *slot;
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Ctlr *ctlr;
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if(arg == nil)
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return;
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slot = arg;
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ctlr = slot->ctlr;
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if(slot->id != 0){
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Ctlr *ctlr = slot->ctlr;
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qlock(&ctlr->slotlock);
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ctlrcmd(ctlr, CR_DISABLESLOT | (slot->id<<24), 0, 0, nil);
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ctlr->dcba[slot->id] = 0;
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ctlr->slot[slot->id] = nil;
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if(ctlr->slot != nil && ctlr->slot[slot->id] == slot){
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ctlrcmd(ctlr, CR_DISABLESLOT | (slot->id<<24), 0, 0, nil);
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ctlr->dcba[slot->id] = 0;
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ctlr->slot[slot->id] = nil;
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}
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qunlock(&ctlr->slotlock);
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}
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freering(&slot->epr[0]);
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@ -843,6 +925,8 @@ allocslot(Ctlr *ctlr, Udev *dev)
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freeslot(slot);
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nexterror();
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}
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if(ctlr->slot == nil)
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error(Erecover);
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slot->ibase = mallocalign(32*33 << ctlr->csz, 64, 0, ctlr->pagesize);
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slot->obase = mallocalign(32*32 << ctlr->csz, 64, 0, ctlr->pagesize);
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if(slot->ibase == nil || slot->obase == nil)
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@ -1065,7 +1149,8 @@ epopen(Ep *ep)
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if(ep->dev->isroot)
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return;
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if(needrecover(ctlr))
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error(Erecover);
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io = malloc(sizeof(Epio)*2);
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if(io == nil)
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error(Enomem);
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@ -1171,6 +1256,8 @@ isowrite(Ep *ep, uchar *p, long n)
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}
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µ = io->period;
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ctlr = ep->hp->aux;
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if(needrecover(ctlr))
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error(Erecover);
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for(i = io->frame;; i++){
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for(;;){
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m = (int)(io->ring->wp - io->ring->rp);
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@ -1439,10 +1526,13 @@ static int
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portstatus(Hci *hp, int port)
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{
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Ctlr *ctlr = hp->aux;
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Port *pp = &ctlr->port[port-1];
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u32int psc, ps = 0;
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u32int psc, ps;
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psc = pp->reg[PORTSC];
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if(ctlr->port == nil || needrecover(ctlr))
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return 0;
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ps = 0;
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psc = ctlr->port[port-1].reg[PORTSC];
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if(psc & CCS) ps |= HPpresent;
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if(psc & PED) ps |= HPenable;
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if(psc & OCA) ps |= HPovercurrent;
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@ -1488,13 +1578,14 @@ static int
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portreset(Hci *hp, int port, int on)
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{
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Ctlr *ctlr = hp->aux;
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Port *pp = &ctlr->port[port-1];
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if(ctlr->port == nil || needrecover(ctlr))
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return 0;
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if(on){
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pp->reg[PORTSC] |= PR;
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ctlr->port[port-1].reg[PORTSC] |= PR;
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tsleep(&up->sleep, return0, nil, 200);
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}
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return 0;
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}
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