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added support for 32 bit MSI

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This commit is contained in:
aiju 2011-05-17 16:51:30 +00:00
parent e7e04b5cbb
commit da5d6db6f5
1 changed files with 6 additions and 4 deletions
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10
sys/src/9/pc/mp.c
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@ -883,13 +883,14 @@ mpintrenablex(Vctl* v, int tbdf)
enum { enum {
MSICtrl = 0x02, /* message control register (16 bit) */ MSICtrl = 0x02, /* message control register (16 bit) */
MSIAddr = 0x04, /* message address register (64 bit) */ MSIAddr = 0x04, /* message address register (64 bit) */
MSIData = 0x0C, /* message data register (16 bit) */ MSIData32 = 0x08, /* message data register for 32 bit MSI (16 bit) */
MSIData64 = 0x0C, /* message data register for 64 bit MSI (16 bit) */
}; };
static int static int
msiintrenable(Vctl *v) msiintrenable(Vctl *v)
{ {
int tbdf, vno, cap, cpu; int tbdf, vno, cap, cpu, ok64;
Pcidev *pci; Pcidev *pci;
if(getconf("*msi") == nil) if(getconf("*msi") == nil)
@ -913,9 +914,10 @@ msiintrenable(Vctl *v)
vno = allocvector(); vno = allocvector();
cpu = mpintrcpu(); cpu = mpintrcpu();
ok64 = (pcicfgr16(pci, cap + MSICtrl) & (1<<7)) != 0;
pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12)); pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
pcicfgw32(pci, cap + MSIAddr + 4, 0); if(ok64) pcicfgw32(pci, cap + MSIAddr + 4, 0);
pcicfgw16(pci, cap + MSIData, vno | (1<<14)); pcicfgw16(pci, cap + ok64 ? MSIData64 : MSIData32, vno | (1<<14));
pcicfgw16(pci, cap + MSICtrl, 1); pcicfgw16(pci, cap + MSICtrl, 1);
print("msiintrenable: success with tbdf %.8x, vector %d, cpu %d\n", tbdf, vno, cpu); print("msiintrenable: success with tbdf %.8x, vector %d, cpu %d\n", tbdf, vno, cpu);
v->isr = lapicisr; v->isr = lapicisr;