Scan PCI via kernel in aux/vga
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taruti
parent
a0a1082dbf
commit
d9b80de6d5
1 changed files with 51 additions and 166 deletions
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@ -28,183 +28,68 @@ static Pcidev* pciroot;
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static Pcidev* pcilist;
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static Pcidev* pcitail;
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static int pcicfgrw32(int, int, int, int);
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static int
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pciscan(int bno, Pcidev** list)
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static void
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pcicfginit(void)
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{
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ulong v;
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Pcidev *p, *head, *tail;
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int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
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Dir *d;
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int fd, i, j, n, bno, dno, fno;
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char buf[1024], *s;
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Pcidev *p;
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maxubn = bno;
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head = nil;
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tail = nil;
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for(dno = 0; dno <= pcimaxdno; dno++){
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maxfno = 0;
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for(fno = 0; fno <= maxfno; fno++){
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/*
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* For this possible device, form the bus+device+function
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* triplet needed to address it and try to read the vendor
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* and device ID. If successful, allocate a device struct
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* and start to fill it in with some useful information from
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* the device's configuration space.
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*/
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tbdf = MKBUS(BusPCI, bno, dno, fno);
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l = pcicfgrw32(tbdf, PciVID, 0, 1);
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if(l == 0xFFFFFFFF || l == 0)
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continue;
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pcicfgmode = 0x666;
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trace("pcicfginit\n");
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fd = open("#$/pci", OREAD);
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if(fd < 0)
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return;
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if((n = dirreadall(fd, &d)) < 0)
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return;
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close(fd);
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for(i=0; i<n; i++) {
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int nl = strlen(d[i].name);
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if(d[i].name[nl-3] == 'r' && d[i].name[nl-2] == 'a' && d[i].name[nl-1] == 'w' ) {
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trace("pci device %s\n",d[i].name);
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sprint(buf, "#$/pci/%s", d[i].name);
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if((fd = open(buf, OREAD)) < 0)
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return;
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if((read(fd, buf, 0x30)) <= 0)
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return;
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close(fd);
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bno = strtoul(d[i].name, &s, 10);
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dno = strtoul(s+1, &s, 10);
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fno = strtoul(s+1, nil, 10);
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trace("\t-> %d %d %d\n",bno, dno, fno);
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p = mallocz(sizeof(*p), 1);
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p->tbdf = tbdf;
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p->vid = l;
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p->did = l>>16;
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p->rid = pcicfgr8(p, PciRID);
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p->tbdf = MKBUS(BusPCI, bno, dno, fno);
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p->vid = *(ulong*)(buf);
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p->did = *(ushort*)(buf+2);
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p->rid = *(uchar*)(buf+PciRID);
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p->intl = *(uchar*)(buf+PciINTL);
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p->ccru = *(ushort*)(buf+PciCCRu);
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int rno = PciBAR0 - 4;
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for(j = 0; j < nelem(p->mem); j++){
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rno += 4;
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p->mem[j].bar = pcicfgr32(p, rno);
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pcicfgw32(p, rno, -1);
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ulong v = pcicfgr32(p, rno);
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pcicfgw32(p, rno, p->mem[i].bar);
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p->mem[j].size = -(v & ~0xF);
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trace("\t->mem[%d] = %p %d\n", j, p->mem[j].bar, p->mem[j].size);
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}
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if(pcilist != nil)
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pcitail->list = p;
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else
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pcilist = p;
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pcitail = p;
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p->intl = pcicfgr8(p, PciINTL);
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p->ccru = pcicfgr16(p, PciCCRu);
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/*
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* If the device is a multi-function device adjust the
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* loop count so all possible functions are checked.
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*/
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hdt = pcicfgr8(p, PciHDT);
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if(hdt & 0x80)
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maxfno = MaxFNO;
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/*
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* If appropriate, read the base address registers
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* and work out the sizes.
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*/
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switch(p->ccru>>8){
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case 0x01: /* mass storage controller */
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case 0x02: /* network controller */
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case 0x03: /* display controller */
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case 0x04: /* multimedia device */
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case 0x07: /* simple communication controllers */
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case 0x08: /* base system peripherals */
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case 0x09: /* input devices */
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case 0x0A: /* docking stations */
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case 0x0B: /* processors */
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case 0x0C: /* serial bus controllers */
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if((hdt & 0x7F) != 0)
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break;
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rno = PciBAR0 - 4;
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for(i = 0; i < nelem(p->mem); i++){
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rno += 4;
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p->mem[i].bar = pcicfgr32(p, rno);
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pcicfgw32(p, rno, -1);
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v = pcicfgr32(p, rno);
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pcicfgw32(p, rno, p->mem[i].bar);
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p->mem[i].size = -(v & ~0xF);
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}
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break;
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case 0x00:
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case 0x05: /* memory controller */
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case 0x06: /* bridge device */
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default:
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break;
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}
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if(head != nil)
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tail->link = p;
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else
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head = p;
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tail = p;
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}
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}
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*list = head;
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for(p = head; p != nil; p = p->link){
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/*
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* Find PCI-PCI bridges and recursively descend the tree.
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*/
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if(p->ccru != ((0x06<<8)|0x04))
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continue;
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/*
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* If the secondary or subordinate bus number is not initialised
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* try to do what the PCI BIOS should have done and fill in the
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* numbers as the tree is descended. On the way down the subordinate
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* bus number is set to the maximum as it's not known how many
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* buses are behind this one; the final value is set on the way
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* back up.
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*/
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sbn = pcicfgr8(p, PciSBN);
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ubn = pcicfgr8(p, PciUBN);
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if(sbn == 0 || ubn == 0){
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sbn = maxubn+1;
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/*
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* Make sure memory, I/O and master enables are off,
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* set the primary, secondary and subordinate bus numbers
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* and clear the secondary status before attempting to
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* scan the secondary bus.
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*
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* Initialisation of the bridge should be done here.
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*/
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pcicfgw32(p, PciPCR, 0xFFFF0000);
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l = (MaxUBN<<16)|(sbn<<8)|bno;
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pcicfgw32(p, PciPBN, l);
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pcicfgw16(p, PciSPSR, 0xFFFF);
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maxubn = pciscan(sbn, &p->bridge);
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l = (maxubn<<16)|(sbn<<8)|bno;
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pcicfgw32(p, PciPBN, l);
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}
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else{
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maxubn = ubn;
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pciscan(sbn, &p->bridge);
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}
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}
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return maxubn;
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}
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static void
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pcicfginit(void)
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{
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#ifdef kernel
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char *p;
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#endif /* kernel */
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int bno;
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Pcidev **list;
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if(pcicfgmode == -1){
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/*
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* Try to determine which PCI configuration mode is implemented.
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* Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
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* a DWORD at 0xCF8 and another at 0xCFC and will pass through
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* any non-DWORD accesses as normal I/O cycles. There shouldn't be
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* a device behind these addresses so if Mode2 accesses fail try
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* for Mode1 (which is preferred, Mode2 is deprecated).
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*/
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outportb(PciCSE, 0);
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if(inportb(PciCSE) == 0){
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pcicfgmode = 2;
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pcimaxdno = 15;
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}
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else{
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outportl(PciADDR, 0);
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if(inportl(PciADDR) == 0){
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pcicfgmode = 1;
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pcimaxdno = 31;
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}
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}
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if(pcicfgmode > 0){
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list = &pciroot;
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for(bno = 0; bno < 256; bno++){
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bno = pciscan(bno, list);
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while(*list)
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list = &(*list)->link;
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}
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trace("\t-> did=%X vid=%X rid=%X intl=%d ccru=%X\n",p->did, p->vid, p->rid,p->intl, p->ccru);
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}
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}
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}
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