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etherigbe: spi eeprom support (thanks echoline)

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This commit is contained in:
cinap_lenrek 2015-05-20 09:49:27 +02:00
parent 6198954859
commit d8487e98c6
1 changed files with 65 additions and 25 deletions
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90
sys/src/9/pc/etherigbe.c
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@ -1572,6 +1572,12 @@ at93c46io(Ctlr* ctlr, char* op, int data)
else else
r = i; r = i;
continue; continue;
case 'H':
eecd |= Do;
continue;
case 'h':
eecd &= ~Do;
continue;
case 'I': /* assert data input */ case 'I': /* assert data input */
eecd |= Di; eecd |= Di;
break; break;
@ -1586,7 +1592,10 @@ at93c46io(Ctlr* ctlr, char* op, int data)
break; break;
} }
csr32w(ctlr, Eecd, eecd); csr32w(ctlr, Eecd, eecd);
microdelay(50); if (eecd & Spi)
microdelay(1);
else
microdelay(50);
} }
if(loop >= 0) if(loop >= 0)
return -1; return -1;
@ -1600,17 +1609,8 @@ at93c46r(Ctlr* ctlr)
char rop[20]; char rop[20];
int addr, areq, bits, data, eecd, i; int addr, areq, bits, data, eecd, i;
eecd = csr32r(ctlr, Eecd);
if(eecd & Spi){
print("igbe: SPI EEPROM access not implemented\n");
return 0;
}
if(eecd & (Eeszaddr|Eesz256))
bits = 8;
else
bits = 6;
sum = 0; sum = 0;
eecd = csr32r(ctlr, Eecd);
switch(ctlr->id){ switch(ctlr->id){
default: default:
@ -1641,23 +1641,63 @@ at93c46r(Ctlr* ctlr)
} }
break; break;
} }
snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
for(addr = 0; addr < 0x40; addr++){ if(eecd & Spi){
/* for(i = 0; i < 1000; i++){
* Read a word at address 'addr' from the Atmel AT93C46 at93c46io(ctlr, "H :8HDCc;", 0x05);
* 3-Wire Serial EEPROM or compatible. The EEPROM access is data = at93c46io(ctlr, "h :8COc;", 0);
* controlled by 4 bits in Eecd. See the AT93C46 datasheet
* for protocol details. if (!(data & 0x1))
*/ break;
if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
print("igbe: can't set EEPROM address 0x%2.2X\n", addr); microdelay(5);
at93c46io(ctlr, "Ss", 0);
}
if(i == 1000){
print("igbe: SPI EEPROM not ready\n");
goto release; goto release;
} }
data = at93c46io(ctlr, ":16COc;", 0);
at93c46io(ctlr, "sic", 0); at93c46io(ctlr, "Ss H :8HDCc;", 0x03);
ctlr->eeprom[addr] = data;
sum += data; if(eecd & Eeszaddr)
bits = 16;
else
bits = 8;
snprint(rop, sizeof(rop), "H :%dHDCc;", bits);
if(at93c46io(ctlr, rop, 0) != 0){
print("igbe: can't set EEPROM address 0x00\n");
goto release;
}
for(addr = 0; addr < 0x40; addr++){
data = at93c46io(ctlr, "h :16COc;", 0);
ctlr->eeprom[addr] = (data >> 8) | (data << 8);
sum += ctlr->eeprom[addr];
}
} else {
if(eecd & (Eeszaddr|Eesz256))
bits = 8;
else
bits = 6;
snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
for(addr = 0; addr < 0x40; addr++){
/*
* Read a word at address 'addr' from the Atmel AT93C46
* 3-Wire Serial EEPROM or compatible. The EEPROM access is
* controlled by 4 bits in Eecd. See the AT93C46 datasheet
* for protocol details.
*/
if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
goto release;
}
data = at93c46io(ctlr, ":16COc;", 0);
at93c46io(ctlr, "sic", 0);
ctlr->eeprom[addr] = data;
sum += data;
}
} }
release: release: