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i2c(3): fix typos, thanks quinq

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cinap_lenrek 2022-07-17 14:43:46 +00:00
parent 06d7118e94
commit ccbabf1c16
1 changed files with 10 additions and 11 deletions
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21
sys/man/3/i2c
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@ -8,7 +8,6 @@ i2c \- I²C Bus Interface
.nf .nf
.BI /dev/ bus /i2c. n .ctl .BI /dev/ bus /i2c. n .ctl
.BI /dev/ bus /i2c. n .data .BI /dev/ bus /i2c. n .data
.fi
.SH DESCRIPTION .SH DESCRIPTION
The I²C (Inter-Integrated Circuit) bus is a serial bus standard The I²C (Inter-Integrated Circuit) bus is a serial bus standard
invented by Philips. invented by Philips.
@ -19,21 +18,21 @@ The bus requires only a single data signal
a clock signal a clock signal
.I SDC .I SDC
and ground. and ground.
Devices on the bus have 7-bit or 10-bit addreesses, which is Devices on the bus have 7-bit or 10-bit addresses, which is
determined by the device (see the datasheet). determined by the device (see the datasheet).
Every device monitors the bus and waits for the master to initiate Every device monitors the bus and waits for the master to initiate
a transaction. a transaction.
Each transaction starts with the master sending the target device address Each transaction starts with the master sending the target device address
and direction bit and the device is acknowledging each byte with a direction bit and the device acknowledges each byte
received if its address matched. received if its address matched.
Depending on the device, more bytes must be transmitted after the Depending on the device, more bytes must be transmitted after the
.IR device-address . .IR device-address .
For example, to encode a register number an memory offset. For example, encoding a register number at a memory offset.
We refer to these bytes as the We refer to these bytes as the
.IR sub-address . .IR sub-address .
After the address phase, the data phase begins where After the address phase, the data phase begins where
zero or more data bytes are eigther transmitted or received zero or more data bytes are either transmitted or received
depending on the transactoin direction. depending on the transaction direction.
.PP .PP
This driver supports multiple buses (controllers) to be registered This driver supports multiple buses (controllers) to be registered
by platform specific code in the kernel. by platform specific code in the kernel.
@ -46,9 +45,9 @@ on a bus, which is done when accessing the
directory. directory.
.PP .PP
Platform specific code can also register individual devices, Platform specific code can also register individual devices,
supplying a meaningfull device configuration. supplying a meaningful device configuration.
It can also be neccesary to manually register devices if It can also be necessary to manually register devices if
the device has been disabled by a enable signal or the device has been disabled by an enable signal or
otherwise inhibited during enumeration. otherwise inhibited during enumeration.
.PP .PP
Each device appears as a control ( Each device appears as a control (
@ -67,12 +66,12 @@ The data file is used to initiate transactions to the device.
The initial The initial
.I sub-address .I sub-address
bytes sent are derived from the file position according to the device bytes sent are derived from the file position according to the device
configuration and the length of the data phase is controlled by configuration, and the length of the data phase is controlled by
the requested read or write size. the requested read or write size.
The requested size might be truncated by the driver if The requested size might be truncated by the driver if
the request exceeds the logical file-size. the request exceeds the logical file-size.
.PP .PP
The control-file provides access the device configuration. The control-file provides access to the device configuration.
When read, When read,
it reproduces this configuration in text form. it reproduces this configuration in text form.
The following text lines are accepted when written to the control-file: The following text lines are accepted when written to the control-file: