zymq: lilu dallas, multicore
implement multiprocessor support.
This commit is contained in:
parent
e08cc06517
commit
cb2103879e
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@ -140,7 +140,6 @@ struct Mach
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Proc* readied; /* for runproc */
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ulong schedticks; /* next forced context switch */
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int cputype;
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ulong delayloop;
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/* stats */
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@ -9,6 +9,7 @@ uintptr cankaddr(uintptr);
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void procsave(Proc *);
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void procrestore(Proc *);
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void idlehands(void);
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void sendevent(void);
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void coherence(void);
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void procfork(Proc *);
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void procsetup(Proc *);
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@ -37,7 +38,9 @@ uintptr getdfar(void);
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void links(void);
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void* vmap(uintptr, ulong);
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void timerinit(void);
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void synccycles(void);
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void setpmcr(ulong);
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void setpmcnten(ulong);
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void* tmpmap(uintptr);
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void tmpunmap(void*);
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void flushpg(void *);
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@ -44,6 +44,9 @@ intrinit(void)
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mpcore[ICCICR] = 7;
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mpcore[ICCBPR] = 3;
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mpcore[ICCPMR] = 255;
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if(m->machno != 0)
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return;
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/* disable all irqs and clear any pending interrupts */
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for(i = 0; i < NINTR/32; i++){
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@ -66,7 +69,7 @@ intrenable(int irq, void (*f)(Ureg *, void *), void *arg, int type, char *name)
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panic("intrenable: invalid irq %d", irq);
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if(type != LEVEL && type != EDGE)
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panic("intrenable: invalid type %d", type);
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if(irqs[irq].f != nil)
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if(irqs[irq].f != nil && irqs[irq].f != f)
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panic("intrenable: handler already assigned");
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if(irq >= NPRIVATE){
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e = &mpcore[ICDIPTR + (irq >> 2)];
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@ -18,7 +18,7 @@ _start0:
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PUTC('l')
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MOVW $SECSZ, R0
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MOVW $(CPU0L1-KZERO), R4
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MOVW $(MACHL1(0)-KZERO), R4
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MOVW $KZERO, R1
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ADD R1>>(SECSH-2), R4, R1
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MOVW $(L1SEC|L1CACHED|L1KERRW), R2
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@ -42,13 +42,20 @@ _start2:
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BGE _start2
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MOVW $(UART_BASE|L2VALID|L2DEVICE|L2KERRW), R0
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MOVW $(VMAPL2 - KZERO), R1
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MOVW $(VMAPL2-KZERO), R1
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MOVW R0, (R1)
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PUTC('n')
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MOVW $(MACH(0)-KZERO), R(Rmach)
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_start3:
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/* enable MMU permission checking */
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MOVW $0x55555555, R0
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MCR 15, 0, R0, C(3), C(0), 0
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MOVW $0, R0
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MCR 15, 0, R0, C(8), C(7), 0
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MOVW $(CPU0L1 - KZERO | TTBATTR), R1
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ADD $TTBATTR, R4, R1
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MCR 15, 0, R1, C(2), C(0), 0
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MOVW $0x20c5047b, R1
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MOVW $_virt(SB), R2
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@ -59,17 +66,18 @@ _start2:
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TEXT _virt(SB), $-4
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DSB
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ISB
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MOVW $(MACH(0) + MACHSIZE), R13
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MOVW $(MACH(0) + 12), R0
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ADD $KZERO, R(Rmach)
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MOVW R(Rmach), R13
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ADD $MACHSIZE, R13
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MOVW R(Rmach), R0
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ADD $12, R0
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BL loadsp(SB)
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MOVW $vectors(SB), R1
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MCR 15, 0, R1, C(12), C(0)
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/* enable MMU permission checking */
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MOVW $0x55555555, R0
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MCR 15, 0, R0, C(3), C(0), 0
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/* enable maths coprocessors in CPACR but disable them in FPEXC */
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MRC 15, 0, R0, C(1), C(0), 2
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ORR $(15<<20), R0
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@ -96,14 +104,25 @@ TEXT _virt(SB), $-4
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MOVW $(VMAP+0x30), R8
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PUTC('9')
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/* kernel Mach* in TPIDRPRW */
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MCR 15, 0, R(Rmach), C(13), C(0), 4
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MOVW $setR12(SB), R12
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MOVW $MACH(0), R(Rmach)
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MOVW $0, R(Rup)
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BL main(SB)
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B idlehands(SB)
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BL _div(SB) /* hack to load _div */
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TEXT mpbootstrap(SB), $-4
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MOVW $0xE0001030, R8
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PUTC('M')
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PUTC('P')
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MOVW $(MACH(1)-KZERO), R(Rmach)
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MOVW $(MACHL1(1)-KZERO), R4
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B _start3
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TEXT touser(SB), $-4
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CPS(CPSID)
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@ -238,6 +257,10 @@ TEXT idlehands(SB), $0
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WFE
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RET
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TEXT sendevent(SB), $0
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SEV
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RET
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TEXT ttbget(SB), $0
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MRC 15, 0, R0, C(2), C(0), 0
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BIC $0x7f, R0
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@ -282,6 +305,10 @@ TEXT setpmcr(SB), $0
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MCR 15, 0, R0, C(9), C(12), 0
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RET
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TEXT setpmcnten(SB), $0
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MCR 15, 0, R0, C(9), C(12), 1
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RET
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TEXT perfticks(SB), $0
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MRC 15, 0, R0, C(9), C(13), 0
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RET
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@ -453,3 +480,4 @@ TEXT palookur(SB), $0
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DSB
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MRC 15, 0, R0, C(7), C(4), 0
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RET
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@ -39,7 +39,8 @@ _exc:
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SUB $(18*4), R13
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MOVM.IA [R0-R14], (R13)
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MOVW $MACH(0), R(Rmach) /* FIXME */
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/* get Mach* from TPIDRPRW */
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MRC 15, 0, R(Rmach), C(13), C(0), 4
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MOVW 8(R(Rmach)), R(Rup)
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MOVW $setR12(SB), R12
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@ -79,7 +80,8 @@ TEXT _vsvc(SB), $-4
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MOVM.DB.S [R0-R14], (R13)
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SUB $(15*4), R13
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MOVW $MACH(0), R(Rmach) /* FIXME */
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/* get Mach* from TPIDRPRW */
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MRC 15, 0, R(Rmach), C(13), C(0), 4
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MOVW 8(R(Rmach)), R(Rup)
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MOVW $setR12(SB), R12
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@ -182,9 +182,9 @@ confinit(void)
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int i;
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conf.nmach = 1;
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conf.nproc = 100;
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conf.nproc = 2000;
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conf.ialloc = 16*1024*1024;
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conf.nimage = conf.nproc;
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conf.nimage = 200;
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conf.mem[0].base = PGROUND((ulong)end - KZERO);
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conf.mem[0].limit = 1024*1024*1024;
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conf.npage = 0;
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@ -346,10 +346,64 @@ isaconfig(char *, int, ISAConf*)
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return 1;
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}
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void
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cpuidprint(void)
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{
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print("\ncpu%d: %dMHz ARM Cortex-A9\n", m->machno, m->cpumhz);
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}
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void
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mpinit(void)
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{
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extern void mpbootstrap(void); /* l.s */
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Mach *m1;
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ulong *v;
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int i;
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if(getconf("*nomp"))
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return;
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conf.nmach = 2;
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conf.copymode = 1;
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m1 = MACHP(1);
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memset(m1, 0, MACHSIZE);
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m1->machno = 1;
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m1->l1.pa = MACHL1(m1->machno)-KZERO;
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m1->l1.va = KADDR(m1->l1.pa);
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memset(m1->l1.va, 0, L1SZ);
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for(i=0; i<L1X(VMAPSZ); i++)
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m1->l1.va[L1X(VMAP)+i] = m->l1.va[L1X(VMAP)+i];
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for(i=0; i<L1X(-KZERO); i++)
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m1->l1.va[L1X(KZERO)+i] = m->l1.va[L1X(KZERO)+i];
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coherence();
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cleandse((uchar*)KZERO, (uchar*)0xFFFFFFFF);
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v = tmpmap(0xFFFFF000);
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v[0xFF0/4] = PADDR(mpbootstrap);
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coherence();
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cleandse(v, (uchar*)v+BY2PG);
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tmpunmap(v);
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sendevent();
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synccycles();
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}
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void
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main(void)
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{
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active.machs = 1;
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active.machs |= (1 << m->machno);
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if(m->machno != 0){
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mmuinit();
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intrinit();
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timerinit();
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cpuidprint();
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synccycles();
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timersinit();
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schedinit();
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return;
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}
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uartinit();
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mmuinit();
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l2init();
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@ -361,6 +415,7 @@ main(void)
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xinit();
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printinit();
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quotefmtinstall();
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cpuidprint();
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sanity();
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todinit();
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timersinit();
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@ -376,5 +431,6 @@ main(void)
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swapinit();
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screeninit();
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userinit();
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mpinit();
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schedinit();
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}
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@ -40,8 +40,8 @@
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#define MACHSIZE 8192
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#define MACH(n) (KZERO+(n)*MACHSIZE)
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#define MACHP(n) ((Mach *)MACH(n))
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#define CPU0L1 ROUND(MACH(MAXMACH), L1SZ)
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#define VMAPL2 (CPU0L1 + L1SZ)
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#define MACHL1(n) (ROUND(MACH(MAXMACH), L1SZ) + (n)*L1SZ)
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#define VMAPL2 MACHL1(MAXMACH)
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#define VMAPL2SZ (L2SZ * (VMAPSZ / SECSZ))
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#define TMAPL2(n) (VMAPL2 + VMAPL2SZ + (n) * L2SZ)
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#define TMAPL2SZ (MAXMACH * L2SZ)
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@ -80,6 +80,7 @@
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#define DSB WORD $0xf57ff04f
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#define ISB WORD $0xf57ff06f
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#define WFE WORD $0xe320f002
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#define SEV WORD $0xe320f004
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#define CPS(m) WORD $(0xf1000000|(m))
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#define CPSMODE (1<<17)
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#define CPSIE (3<<6|2<<18)
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@ -121,4 +122,4 @@
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#define L2WRITE 0
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#define L2LOCAL (1<<11)
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#define TTBATTR (1<<6|1<<3)
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#define TTBATTR (1<<6|1<<3|1<<1)
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@ -12,10 +12,13 @@ mmuinit(void)
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{
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m->l1.pa = ttbget();
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m->l1.va = KADDR(m->l1.pa);
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mpcore = vmap(MPCORE_BASE, 0x2000);
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slcr = vmap(SLCR_BASE, 0x1000);
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memset((uchar*)TMAPL2(m->machno), 0, TMAPL2SZ);
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m->l1.va[L1X(TMAP)] = PADDR(TMAPL2(m->machno)) | L1PT;
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incref(&m->l1);
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if(mpcore != nil)
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return;
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mpcore = vmap(MPCORE_BASE, 0x2000);
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slcr = vmap(SLCR_BASE, 0x1000);
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}
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void
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@ -38,29 +41,28 @@ l1alloc(void)
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int s;
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s = splhi();
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if(m->l1free != nil){
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p = m->l1free;
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p = m->l1free;
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if(p != nil){
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m->l1free = p->next;
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p->next = nil;
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m->l1free = m->l1free->next;
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m->nfree--;
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splx(s);
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return p;
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}else{
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p = smalloc(sizeof(L1));
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for(;;){
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p->va = mallocalign(L1SZ, L1SZ, 0, 0);
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if(p->va != nil)
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break;
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if(!waserror()){
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resrcwait("no memory for L1 table");
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poperror();
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}
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}
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memmove(p->va, m->l1.va, L1SZ);
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p->pa = PADDR(p->va);
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splx(s);
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return p;
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}
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splx(s);
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p = smalloc(sizeof(L1));
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for(;;){
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p->va = mallocalign(L1SZ, L1SZ, 0, 0);
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if(p->va != nil)
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break;
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if(!waserror()){
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resrcwait("no memory for L1 table");
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poperror();
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}
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}
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p->pa = PADDR(p->va);
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memmove(p->va, m->l1.va, L1SZ);
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return p;
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}
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static void
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@ -89,11 +91,9 @@ upallocl1(void)
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p = l1alloc();
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s = splhi();
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if(up->l1 != nil)
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l1free(p);
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else{
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up->l1 = p;
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l1switch(p, 1);
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}
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panic("upalloc1: up->l1 != nil");
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up->l1 = p;
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l1switch(p, 1);
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splx(s);
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}
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@ -114,6 +114,7 @@ l2free(Proc *proc)
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*t = 0;
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l = &p->next;
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}
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proc->l1->va[L1X(TMAP)] = 0;
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*l = proc->mmufree;
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proc->mmufree = proc->mmuused;
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proc->mmuused = 0;
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@ -139,6 +140,7 @@ putmmu(uintptr va, uintptr pa, Page *pg)
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ulong *e;
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ulong *l2;
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PTE old;
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char *ctl;
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uintptr l2p;
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int s;
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@ -178,17 +180,17 @@ putmmu(uintptr va, uintptr pa, Page *pg)
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splx(s);
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if((old & L2VALID) != 0)
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flushpg((void *) va);
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if(pg->cachectl[0] == PG_TXTFLUSH){
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ctl = &pg->cachectl[m->machno];
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if(*ctl == PG_TXTFLUSH){
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cleandse((void *) va, (void *) (va + BY2PG));
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invalise((void *) va, (void *) (va + BY2PG));
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pg->cachectl[0] = PG_NOFLUSH;
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*ctl = PG_NOFLUSH;
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}
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}
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void
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checkmmu(uintptr, uintptr)
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{
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print("checkmmu\n");
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}
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void
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@ -286,7 +288,7 @@ kmap(Page *page)
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e = &up->l1->va[L1X(KMAP)];
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if((*e & 3) == 0){
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if(up->kmaptable != nil)
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panic("kmaptable");
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panic("kmaptable != nil");
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up->kmaptable = newpage(0, 0, 0);
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s = splhi();
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v = tmpmap(up->kmaptable->pa);
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@ -300,7 +302,7 @@ kmap(Page *page)
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return (KMap *) KMAP;
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}
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if(up->kmaptable == nil)
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panic("kmaptable");
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panic("kmaptable == nil");
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e = (ulong *) (KMAP + NKMAP * BY2PG);
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for(i = 0; i < NKMAP; i++)
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if((e[i] & 3) == 0){
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@ -338,7 +340,6 @@ void *
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tmpmap(ulong pa)
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{
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ulong *u, *ub, *ue;
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void *v;
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if(islo())
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panic("tmpmap: islow %#p", getcallerpc(&pa));
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@ -349,9 +350,13 @@ tmpmap(ulong pa)
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for(u = ub; u < ue; u++)
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if((*u & 3) == 0){
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*u = pa | L2VALID | L2CACHED | L2KERRW;
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assert(m->l1.va[L1X(TMAP)] != 0);
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if(up != nil && up->l1 != nil)
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up->l1->va[L1X(TMAP)] = m->l1.va[L1X(TMAP)];
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coherence();
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v = (void *) ((u - ub) * BY2PG + TMAP);
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return v;
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return (void *) ((u - ub) * BY2PG + TMAP);
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}
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panic("tmpmap: full (pa=%#.8lux)", pa);
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return nil;
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@ -361,7 +366,7 @@ void
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tmpunmap(void *v)
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{
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ulong *u;
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||||
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||||
|
||||
if(v >= (void*) KZERO)
|
||||
return;
|
||||
if(v < (void*)TMAP || v >= (void*)(TMAP + TMAPSZ))
|
||||
|
|
|
@ -80,12 +80,39 @@ timerirq(Ureg *u, void *)
|
|||
void
|
||||
timerinit(void)
|
||||
{
|
||||
int mhz;
|
||||
|
||||
mhz = PS_CLK * (slcr[ARM_PLL_CTRL] >> 12 & 0x7f) / (slcr[ARM_CLK_CTRL] >> 8 & 0x3f);
|
||||
timerhz = mhz * 500000;
|
||||
m->cpumhz = PS_CLK * (slcr[ARM_PLL_CTRL] >> 12 & 0x7f) / (slcr[ARM_CLK_CTRL] >> 8 & 0x3f);
|
||||
m->cpuhz = m->cpumhz * 1000000;
|
||||
timerhz = m->cpuhz / 2;
|
||||
mpcore[GTIMERCTL] = TIMERDIV - 1 << 8 | 3;
|
||||
mpcore[LTIMERCTL] = LTIMERDIV - 1 << 8 | 4;
|
||||
intrenable(TIMERIRQ, timerirq, nil, EDGE, "clock");
|
||||
|
||||
/* enable and reset cycle counter register */
|
||||
m->cyclefreq = m->cpuhz;
|
||||
setpmcnten((1<<31));
|
||||
coherence();
|
||||
setpmcr(7);
|
||||
}
|
||||
|
||||
/*
|
||||
* synchronize all cpu's cycle counter registers
|
||||
*/
|
||||
void
|
||||
synccycles(void)
|
||||
{
|
||||
static Ref r1, r2;
|
||||
int s;
|
||||
|
||||
s = splhi();
|
||||
r2.ref = 0;
|
||||
incref(&r1);
|
||||
while(r1.ref != conf.nmach)
|
||||
;
|
||||
setpmcr(7);
|
||||
m->cycleshi = MACHP(0)->cycleshi;
|
||||
incref(&r2);
|
||||
while(r2.ref != conf.nmach)
|
||||
;
|
||||
r1.ref = 0;
|
||||
splx(s);
|
||||
}
|
||||
|
|
|
@ -20,7 +20,7 @@ _dumpstack(Ureg *ureg)
|
|||
iprint("dumpstack disabled\n");
|
||||
return;
|
||||
}
|
||||
iprint("dumpstack\n");
|
||||
iprint("cpu%d: dumpstack\n", m->machno);
|
||||
|
||||
x = 0;
|
||||
x += iprint("ktrace /arm/9zynq %.8lux %.8lux %.8lux <<EOF\n", ureg->pc, ureg->sp, ureg->r14);
|
||||
|
@ -57,7 +57,7 @@ faultarm(Ureg *ureg, ulong fsr, uintptr addr)
|
|||
{
|
||||
int user, insyscall, read, n;
|
||||
static char buf[ERRMAX];
|
||||
|
||||
|
||||
read = (fsr & (1<<11)) == 0;
|
||||
user = userureg(ureg);
|
||||
if(!user){
|
||||
|
@ -88,18 +88,24 @@ faultarm(Ureg *ureg, ulong fsr, uintptr addr)
|
|||
static void
|
||||
mathtrap(Ureg *, ulong)
|
||||
{
|
||||
int s;
|
||||
|
||||
if((up->fpstate & FPillegal) != 0){
|
||||
postnote(up, 1, "sys: floating point in note handler", NDebug);
|
||||
return;
|
||||
}
|
||||
switch(up->fpstate){
|
||||
case FPinit:
|
||||
s = splhi();
|
||||
fpinit();
|
||||
up->fpstate = FPactive;
|
||||
splx(s);
|
||||
break;
|
||||
case FPinactive:
|
||||
s = splhi();
|
||||
fprestore(&up->fpsave);
|
||||
up->fpstate = FPactive;
|
||||
splx(s);
|
||||
break;
|
||||
case FPactive:
|
||||
postnote(up, 1, "sys: floating point error", NDebug);
|
||||
|
@ -138,6 +144,7 @@ trap(Ureg *ureg)
|
|||
postnote(up, 1, "sys: trap: invalid opcode", NDebug);
|
||||
break;
|
||||
}
|
||||
dumpregs(ureg);
|
||||
panic("invalid opcode at pc=%#.8lux lr=%#.8lux", ureg->pc, ureg->r14);
|
||||
break;
|
||||
case PsrMiabt:
|
||||
|
@ -153,7 +160,7 @@ trap(Ureg *ureg)
|
|||
intr(ureg);
|
||||
break;
|
||||
default:
|
||||
print("unknown trap type %ulx\n", ureg->type);
|
||||
iprint("cpu%d: unknown trap type %ulx\n", m->machno, ureg->type);
|
||||
}
|
||||
splhi();
|
||||
if(user){
|
||||
|
@ -408,9 +415,17 @@ dumpstack(void)
|
|||
}
|
||||
|
||||
void
|
||||
dumpregs(Ureg *)
|
||||
dumpregs(Ureg *ureg)
|
||||
{
|
||||
print("dumpregs\n");
|
||||
iprint("trap: %lux psr %8.8lux type %2.2lux pc %8.8lux link %8.8lux\n",
|
||||
ureg->type, ureg->psr, ureg->type, ureg->pc, ureg->link);
|
||||
iprint("R14 %8.8lux R13 %8.8lux R12 %8.8lux R11 %8.8lux R10 %8.8lux\n",
|
||||
ureg->r14, ureg->r13, ureg->r12, ureg->r11, ureg->r10);
|
||||
iprint("R9 %8.8lux R8 %8.8lux R7 %8.8lux R6 %8.8lux R5 %8.8lux\n",
|
||||
ureg->r9, ureg->r8, ureg->r7, ureg->r6, ureg->r5);
|
||||
iprint("R4 %8.8lux R3 %8.8lux R2 %8.8lux R1 %8.8lux R0 %8.8lux\n",
|
||||
ureg->r4, ureg->r3, ureg->r2, ureg->r1, ureg->r0);
|
||||
iprint("pc %#lux link %#lux\n", ureg->pc, ureg->link);
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -476,7 +491,7 @@ procsave(Proc *p)
|
|||
cycles(&t);
|
||||
p->kentry -= t;
|
||||
p->pcycles += t;
|
||||
|
||||
|
||||
l1switch(&m->l1, 0);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue