usbxhci: implement controller handoff, ignore usb3.0 ports, honor pollival for isochronous endpoints
This commit is contained in:
cinap_lenrek
parent
aaf6d7c558
commit
c74538a67e
1 changed files with 172 additions and 99 deletions
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@ -147,6 +147,7 @@ typedef struct Wait Wait;
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typedef struct Ring Ring;
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typedef struct Slot Slot;
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typedef struct Epio Epio;
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typedef struct Port Port;
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struct Wait
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{
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@ -193,6 +194,14 @@ struct Slot
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Ring epr[32];
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};
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struct Port
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{
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char spec[4];
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int proto;
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u32int *reg;
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};
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struct Ctlr
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{
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Pcidev *pcidev;
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@ -200,7 +209,6 @@ struct Ctlr
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u32int *mmio;
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u32int *opr; /* operational registers */
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u32int *prt; /* port register set */
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u32int *rts; /* runtime registers */
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u32int *dba; /* doorbell array */
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@ -213,10 +221,11 @@ struct Ctlr
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Ring er[1]; /* event ring segment */
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Ring cr[1]; /* command ring segment */
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u32int mfwrap;
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u32int µframe;
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QLock slotlock;
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Slot **slot; /* slots by slot id */
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Port *port;
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u32int hccparams;
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@ -239,10 +248,12 @@ struct Epio
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Block *b;
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/* iso */
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int nleft;
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u32int frame;
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u32int period;
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u32int incr;
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u32int tdsz;
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int nleft;
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};
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static char Ebadlen[] = "bad usb request length";
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@ -262,15 +273,14 @@ setrptr64(u32int *reg, u64int pa)
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}
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static u32int
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mfindex(Ctlr *ctlr)
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µframe(Ctlr *ctlr)
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{
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u32int lo, hi;
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u32int µ;
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do {
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hi = ctlr->mfwrap;
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lo = ctlr->rts[MFINDEX];
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} while(hi != ctlr->mfwrap);
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return (lo & (1<<14)-1) | hi<<14;
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µ = (ctlr->rts[MFINDEX] & (1<<14)-1) |
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(ctlr->µframe & ~((1<<14)-1));
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} while((int)(µ - ctlr->µframe) < 0);
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return µ;
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}
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static void
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@ -302,38 +312,78 @@ initring(Ring *r, int shift)
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return r;
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}
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static u32int*
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xecp(Ctlr *ctlr, uchar id, u32int *p)
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{
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u32int x;
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if(p != nil) {
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x = *p;
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goto Next;
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}
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x = ctlr->hccparams>>16;
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if(x == 0)
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return nil;
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p = ctlr->mmio + x;
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while(((x = *p) & 255) != id){
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Next:
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x >>= 8, x &= 255;
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if(x == 0)
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return nil;
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p += x;
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}
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return p;
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}
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static void
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handoff(Ctlr *ctlr)
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{
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u32int *r;
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int i;
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if((r = xecp(ctlr, 1, nil)) == nil)
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return;
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r[0] |= 1<<24; /* request ownership */
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for(i = 0; (r[0] & (1<<16)) != 0 && i<100; i++)
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tsleep(&up->sleep, return0, nil, 10);
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r[1] = 0; /* disable SMI interrupts */
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r[0] &= ~(1<<16); /* in case of timeout */
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}
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static void
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init(Hci *hp)
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{
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Ctlr *ctlr;
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Port *pp;
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u32int *x;
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uchar *p;
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int i;
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int i, j;
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ctlr = hp->aux;
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ctlr->opr = &ctlr->mmio[(ctlr->mmio[CAPLENGTH]&0xFF)/4];
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ctlr->prt = &ctlr->opr[0x400/4];
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ctlr->dba = &ctlr->mmio[ctlr->mmio[DBOFF]/4];
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ctlr->rts = &ctlr->mmio[ctlr->mmio[RTSOFF]/4];
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while(ctlr->opr[USBSTS] & CNR)
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ctlr->hccparams = ctlr->mmio[HCCPARAMS];
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handoff(ctlr);
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for(i=0; (ctlr->opr[USBSTS] & CNR) != 0 && i<100; i++)
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tsleep(&up->sleep, return0, nil, 10);
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ctlr->opr[USBCMD] = HCRST;
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while((ctlr->opr[USBSTS] & (CNR|HCH)) != HCH)
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for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != HCH && i<100; i++)
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tsleep(&up->sleep, return0, nil, 10);
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pcisetbme(ctlr->pcidev);
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pcisetpms(ctlr->pcidev, 0);
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intrenable(ctlr->pcidev->intl, hp->interrupt, hp, ctlr->pcidev->tbdf, hp->type);
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ctlr->hccparams = ctlr->mmio[HCCPARAMS];
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ctlr->csz = (ctlr->hccparams & CSZ) != 0;
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if(ctlr->hccparams & AC64)
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ctlr->setrptr = setrptr64;
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else
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ctlr->setrptr = setrptr32;
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ctlr->pagesize = ctlr->opr[PAGESIZE]<<12;
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ctlr->nscratch = (ctlr->mmio[HCSPARAMS2] >> 27) & 0x1F;
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@ -341,6 +391,24 @@ init(Hci *hp)
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ctlr->nslots = (ctlr->mmio[HCSPARAMS1] >> 0) & 0xFF;
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hp->nports = (ctlr->mmio[HCSPARAMS1] >> 24) & 0xFF;
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ctlr->port = malloc(hp->nports * sizeof(Port));
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for(i=0; i<hp->nports; i++)
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ctlr->port[i].reg = &ctlr->opr[0x400/4 + i*4];
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x = nil;
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while((x = xecp(ctlr, 2, x)) != nil){
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i = x[2]&255;
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j = (x[2]>>8)&255;
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while(j--){
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if(i < 1 || i > hp->nports)
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break;
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pp = &ctlr->port[i-1];
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pp->proto = x[0]>>16;
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memmove(pp->spec, &x[1], 4);
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i++;
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}
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}
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ctlr->slot = malloc((1+ctlr->nslots)*sizeof(ctlr->slot[0]));
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ctlr->dcba = mallocalign((1+ctlr->nslots)*8, 64, 0, ctlr->pagesize);
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if(ctlr->nscratch != 0){
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@ -391,10 +459,9 @@ init(Hci *hp)
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irs[IMOD] = 0;
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}
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ctlr->mfwrap = 0;
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ctlr->µframe = 0;
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ctlr->opr[USBCMD] = RUNSTOP|INTE|HSEE|EWE;
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while(ctlr->opr[USBSTS] & (CNR|HCH))
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for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != 0 && i<100; i++)
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tsleep(&up->sleep, return0, nil, 10);
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}
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@ -580,6 +647,9 @@ interrupt(Ureg*, void *arg)
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Slot *slot;
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u32int *irs, *td, x;
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if(ring->base == nil)
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return;
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irs = &ctlr->rts[IR0];
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x = irs[IMAN];
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if(x & 1) irs[IMAN] = x & 3;
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@ -603,7 +673,8 @@ interrupt(Ureg*, void *arg)
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completering(&slot->epr[(td[3]>>16)-1&31], td);
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break;
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case ER_MFINDEXWRAP:
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ctlr->mfwrap++;
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ctlr->µframe = (ctlr->rts[MFINDEX] & (1<<14)-1) |
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(ctlr->µframe+(1<<14) & ~((1<<14)-1));
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break;
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case ER_HCE:
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iprint("xhci: host controller error: %ux %ux %ux %ux\n",
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@ -787,10 +858,9 @@ initisoio(Epio *io, Ep *ep)
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if(io->ring == nil)
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return;
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io->frame = 0;
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io->incr = (ep->hz<<8)/1000;
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io->period = ep->pollival<<3*(ep->dev->speed == Fullspeed);
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io->incr = (ep->hz*io->period<<8)/8000;
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io->tdsz = (io->incr+255>>8)*ep->samplesz;
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if(io->tdsz > ep->maxpkt*ep->ntds)
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error(Egreg);
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io->b = allocb((io->ring->mask+1)*io->tdsz);
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}
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@ -977,6 +1047,74 @@ epopen(Ep *ep)
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poperror();
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}
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static long
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isoread(Ep *, uchar *, long)
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{
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error(Egreg);
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return 0;
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}
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static long
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isowrite(Ep *ep, uchar *p, long n)
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{
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uchar *s, *d;
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Ctlr *ctlr;
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Epio *io;
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u32int i, µ;
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long m;
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s = p;
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io = (Epio*)ep->aux + OWRITE;
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qlock(io);
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if(waserror()){
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qunlock(io);
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nexterror();
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}
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µ = io->period;
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ctlr = ep->hp->aux;
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for(i = io->frame;; i++){
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for(;;){
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m = (int)(io->ring->wp - io->ring->rp);
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if(m <= 0)
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i = (80 + µframe(ctlr))/µ;
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if(m < io->ring->mask)
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break;
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*io->ring->doorbell = io->ring->id;
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tsleep(&up->sleep, return0, nil, 5);
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}
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m = ((io->incr + (i*io->incr&255))>>8)*ep->samplesz;
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d = io->b->rp + (i&io->ring->mask)*io->tdsz;
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m -= io->nleft, d += io->nleft;
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if(n < m){
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memmove(d, p, n);
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p += n;
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io->nleft += n;
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break;
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}
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memmove(d, p, m);
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p += m, n -= m;
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m += io->nleft, d -= io->nleft;
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io->nleft = 0;
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coherence();
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ilock(io->ring);
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queuetd(io->ring, TR_ISOCH | (i*µ/8 & 0x7ff)<<20 | 1<<5, m, PADDR(d), nil);
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iunlock(io->ring);
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}
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io->frame = i;
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while(io->ring->rp != io->ring->wp){
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int d = (int)(i*µ - µframe(ctlr))/8;
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d -= ep->sampledelay*1000 / ep->hz;
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if(d < 5)
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break;
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*io->ring->doorbell = io->ring->id;
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tsleep(&up->sleep, return0, nil, d);
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}
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qunlock(io);
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poperror();
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return p - s;
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}
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static char*
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unstall(Ring *r)
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{
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@ -1007,77 +1145,6 @@ unstall(Ring *r)
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return nil;
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}
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static long
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isoread(Ep *, uchar *, long)
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{
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error(Egreg);
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return 0;
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}
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static long
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isowrite(Ep *ep, uchar *p, long n)
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{
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uchar *s, *d;
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Ctlr *ctlr;
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Epio *io;
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u32int x;
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long m;
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s = p;
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io = (Epio*)ep->aux + OWRITE;
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qlock(io);
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if(waserror()){
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qunlock(io);
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nexterror();
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}
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ctlr = ep->hp->aux;
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for(x = io->frame;; x++){
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for(;;){
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m = (int)(io->ring->wp - io->ring->rp);
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if(m <= 0)
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x = 10 + mfindex(ctlr)/8;
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if(m < io->ring->mask-1)
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break;
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coherence();
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*io->ring->doorbell = io->ring->id;
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tsleep(&up->sleep, return0, nil, 5);
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}
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m = ((io->incr + (x*io->incr&255))>>8)*ep->samplesz;
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d = io->b->rp + (x&io->ring->mask)*io->tdsz;
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m -= io->nleft, d += io->nleft;
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if(n < m){
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memmove(d, p, n);
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p += n;
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io->nleft += n;
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break;
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}
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memmove(d, p, m);
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p += m, n -= m;
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m += io->nleft, d -= io->nleft;
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io->nleft = 0;
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ilock(io->ring);
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queuetd(io->ring, TR_ISOCH | (x & 0x7ff)<<20 | 1<<5, m, PADDR(d), nil);
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iunlock(io->ring);
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}
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io->frame = x;
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coherence();
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*io->ring->doorbell = io->ring->id;
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qunlock(io);
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poperror();
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for(;;){
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int d = (int)(x - mfindex(ctlr)/8);
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d -= ep->sampledelay*1000 / ep->hz;
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if(d < 5)
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break;
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tsleep(&up->sleep, return0, nil, d);
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}
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return p - s;
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}
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static long
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epread(Ep *ep, void *va, long n)
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{
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@ -1269,9 +1336,13 @@ static int
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portstatus(Hci *hp, int port)
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{
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Ctlr *ctlr = hp->aux;
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u32int psc = ctlr->prt[PORTSC + (port-1)*4];
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Port *pp = &ctlr->port[port-1];
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u32int psc = pp->reg[PORTSC];
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int ps = 0;
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if(memcmp(pp->spec, "USB", 3) != 0 || pp->proto > 0x0200)
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return 0;
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if(psc & CCS) ps |= HPpresent;
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if(psc & PED) ps |= HPenable;
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if(psc & OCA) ps |= HPovercurrent;
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@ -1287,8 +1358,7 @@ portstatus(Hci *hp, int port)
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case 3:
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ps |= HPhigh;
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break;
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case 4:
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/* super speed */
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case 4: /* super speed */
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break;
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}
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}
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@ -1310,10 +1380,13 @@ static int
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portreset(Hci *hp, int port, int on)
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{
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Ctlr *ctlr = hp->aux;
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u32int *r = &ctlr->prt[PORTSC + (port-1)*4];
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Port *pp = &ctlr->port[port-1];
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if(memcmp(pp->spec, "USB", 3) != 0 || pp->proto > 0x0200)
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return 0;
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if(on){
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*r |= PR;
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pp->reg[PORTSC] |= PR;
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tsleep(&up->sleep, return0, nil, 200);
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}
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