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c6f6396faa
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@ -83,9 +83,10 @@ struct Dre { /* descriptor ring entry */
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ulong addr;
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ulong md1; /* status|bcnt */
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ulong md2; /* rcc|rpc|mcnt */
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Block* bp;
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ulong aux;
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};
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enum { /* md1 */
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Enp = 0x01000000, /* end of packet */
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Stp = 0x02000000, /* start of packet */
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@ -120,9 +121,11 @@ struct Ctlr {
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int init; /* initialisation in progress */
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Iblock iblock;
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Block** rb;
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Dre* rdr; /* receive descriptor ring */
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int rdrx;
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Block** tb;
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Dre* tdr; /* transmit descriptor ring */
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int tdrh; /* host index into tdr */
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int tdri; /* interface index into tdr */
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@ -227,7 +230,9 @@ ifstat(Ether* ether, void* a, long n, ulong offset)
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static void
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ringinit(Ctlr* ctlr)
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{
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Block *bp;
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Dre *dre;
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int i;
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/*
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* Initialise the receive and transmit buffer rings.
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@ -235,19 +240,26 @@ ringinit(Ctlr* ctlr)
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*
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* This routine is protected by ctlr->init.
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*/
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if(ctlr->rb == nil)
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ctlr->rb = malloc(Nrdre*sizeof(Block*));
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if(ctlr->rdr == 0){
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ctlr->rdr = xspanalloc(Nrdre*sizeof(Dre), 0x10, 0);
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for(dre = ctlr->rdr; dre < &ctlr->rdr[Nrdre]; dre++){
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dre->bp = iallocb(Rbsize);
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if(dre->bp == nil)
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for(i=0; i<Nrdre; i++){
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bp = iallocb(Rbsize);
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if(bp == nil)
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panic("can't allocate ethernet receive ring");
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dre->addr = PADDR(dre->bp->rp);
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ctlr->rb[i] = bp;
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dre = &ctlr->rdr[i];
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dre->addr = PADDR(bp->rp);
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dre->md2 = 0;
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dre->md1 = Own|(-Rbsize & 0xFFFF);
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dre->aux = 0;
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}
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}
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ctlr->rdrx = 0;
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if(ctlr->tb == nil)
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ctlr->tb = malloc(Ntdre*sizeof(Block*));
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if(ctlr->tdr == 0)
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ctlr->tdr = xspanalloc(Ntdre*sizeof(Dre), 0x10, 0);
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memset(ctlr->tdr, 0, Ntdre*sizeof(Dre));
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@ -312,6 +324,7 @@ txstart(Ether* ether)
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Ctlr *ctlr;
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Block *bp;
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Dre *dre;
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int i;
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ctlr = ether->ctlr;
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@ -330,8 +343,11 @@ txstart(Ether* ether)
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* There's no need to pad to ETHERMINTU
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* here as ApadXmt is set in CSR4.
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*/
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dre = &ctlr->tdr[ctlr->tdrh];
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dre->bp = bp;
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i = ctlr->tdrh;
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if(ctlr->tb[i] != nil)
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break;
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dre = &ctlr->tdr[i];
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ctlr->tb[i] = bp;
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dre->addr = PADDR(bp->rp);
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dre->md2 = 0;
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dre->md1 = Own|Stp|Enp|(-BLEN(bp) & 0xFFFF);
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@ -357,9 +373,9 @@ interrupt(Ureg*, void* arg)
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{
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Ctlr *ctlr;
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Ether *ether;
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int csr0, len;
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int csr0, len, i;
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Dre *dre;
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Block *bp;
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Block *bp, *bb;
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ether = arg;
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ctlr = ether->ctlr;
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@ -388,7 +404,8 @@ intrloop:
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* until a descriptor is encountered still owned by the chip.
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*/
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if(csr0 & Rint){
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dre = &ctlr->rdr[ctlr->rdrx];
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i = ctlr->rdrx;
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dre = &ctlr->rdr[i];
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while(!(dre->md1 & Own)){
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if(dre->md1 & RxErr){
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if(dre->md1 & RxBuff)
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@ -401,10 +418,13 @@ intrloop:
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ctlr->fram++;
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}
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else if(bp = iallocb(Rbsize)){
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bb = ctlr->rb[i];
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ctlr->rb[i] = bp;
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if(bb != nil){
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len = (dre->md2 & 0x0FFF)-4;
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dre->bp->wp = dre->bp->rp+len;
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etheriq(ether, dre->bp, 1);
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dre->bp = bp;
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bb->wp = bb->rp+len;
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etheriq(ether, bb, 1);
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}
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dre->addr = PADDR(bp->rp);
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}
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@ -426,7 +446,8 @@ intrloop:
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if(csr0 & Tint){
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lock(ctlr);
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while(ctlr->ntq){
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dre = &ctlr->tdr[ctlr->tdri];
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i = ctlr->tdri;
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dre = &ctlr->tdr[i];
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if(dre->md1 & Own)
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break;
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@ -443,8 +464,11 @@ intrloop:
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ctlr->txbuff++;
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ether->oerrs++;
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}
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freeb(dre->bp);
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bp = ctlr->tb[i];
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if(bp != nil){
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ctlr->tb[i] = nil;
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freeb(bp);
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}
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ctlr->ntq--;
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ctlr->tdri = NEXT(ctlr->tdri, Ntdre);
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@ -86,11 +86,18 @@ TEXT _warp64<>(SB), 1, $-4
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MOVL DX, PML4O(KZERO)(AX) /* PML4E for KZERO */
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ADDL $PTSZ, AX /* PDP at PML4 + PTSZ */
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ADDL $PTSZ, DX /* PD at PML4 + 2*PTSZ */
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ADDL $PTSZ, DX /* PD0 at PML4 + 2*PTSZ */
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MOVL DX, PDPO(0)(AX) /* PDPE for double-map */
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MOVL DX, PDPO(KZERO)(AX) /* PDPE for KZERO */
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ADDL $PTSZ, AX /* PD at PML4 + 2*PTSZ */
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/*
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* add PDPE for KZERO+1GB early as Vmware
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* hangs when modifying kernel PDP
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*/
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ADDL $PTSZ, DX /* PD1 */
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MOVL DX, PDPO(KZERO+GiB)(AX)
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ADDL $PTSZ, AX /* PD0 at PML4 + 2*PTSZ */
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MOVL $(PTESIZE|PTEGLOBAL|PTEWRITE|PTEVALID), DX
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MOVL DX, PDO(0)(AX) /* PDE for double-map */
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@ -52,13 +52,13 @@
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/*
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* Address spaces. Kernel, sorted by address.
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*/
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#define KZERO (0xffffffff80000000ull) /* 2GB identity map of lower 2GB ram */
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#define KZERO (0xffffffff80000000ull)
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#define KTZERO (KZERO+1*MiB+64*KiB)
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#define VMAP (0xffffffff00000000ull) /* 2GB identity map of upper 2GB ram */
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#define VMAPSIZE (2*GiB)
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#define VMAP (0xffffff0000000000ull)
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#define VMAPSIZE (512*GiB)
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#define KMAP (0xffffff7f00000000ull) /* 2MB for per process temporary kernel mappings */
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#define KMAP (0xfffffe8000000000ull)
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#define KMAPSIZE (2*MiB)
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/*
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#define APBOOTSTRAP (KZERO+0x3000ull) /* AP bootstrap code */
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#define IDTADDR (KZERO+0x10000ull) /* idt */
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#define REBOOTADDR (0x11000) /* reboot code - physical address */
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#define CPU0PML4 (KZERO+0x13000ull)
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#define CPU0PDP (KZERO+0x14000ull)
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#define CPU0PD0 (KZERO+0x15000ull) /* KZERO */
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#define CPU0PD1 (KZERO+0x16000ull) /* KZERO+1GB */
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#define CPU0GDT (KZERO+0x17000ull) /* bootstrap processor GDT */
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#define CPU0MACH (KZERO+0x18000ull) /* Mach for bootstrap processor */
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#define CPU0END (CPU0MACH+MACHSIZE)
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@ -82,8 +82,8 @@ mmuinit(void)
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didmmuinit = 1;
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/* zap double map done by l.s */
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m->pml4[0] = 0;
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m->pml4[512] = 0;
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m->pml4[0] = 0;
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m->tss = mallocz(sizeof(Tss), 1);
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if(m->tss == nil)
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@ -157,7 +157,7 @@ paddr(void *v)
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if(va >= KZERO)
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return va-KZERO;
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if(va >= VMAP)
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return va-(VMAP-(-KZERO));
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return va-VMAP;
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panic("paddr: va=%#p pc=%#p", va, getcallerpc(&v));
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return 0;
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}
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@ -505,12 +505,7 @@ vmap(uintptr pa, int size)
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uintptr va;
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int o;
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if(size <= 0 || pa >= -VMAP)
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panic("vmap: pa=%#p size=%d pc=%#p", pa, size, getcallerpc(&pa));
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if(cankaddr(pa) >= size)
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va = pa+KZERO;
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else
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va = pa+(VMAP-(-KZERO));
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va = pa+VMAP;
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/*
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* might be asking for less than a page.
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*/
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@ -44,7 +44,7 @@ link
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# ether2000 ether8390
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# ether2114x pci
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# ether589 etherelnk3
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# ether79c970 pci
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ether79c970 pci
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# ether8003 ether8390
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# ether8139 pci
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# ether8169 pci ethermii
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@ -44,7 +44,7 @@ link
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# ether2000 ether8390
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# ether2114x pci
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# ether589 etherelnk3
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# ether79c970 pci
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ether79c970 pci
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# ether8003 ether8390
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# ether8139 pci
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# ether8169 pci ethermii
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@ -73,6 +73,7 @@ mpstartap(Apic* apic)
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* PDP between processors.
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*/
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pml4[PTLX(KZERO, 3)] = MACHP(0)->pml4[PTLX(KZERO, 3)];
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pml4[PTLX(VMAP, 3)] = MACHP(0)->pml4[PTLX(VMAP, 3)];
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/* double map */
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pml4[0] = PADDR(pdp0) | PTEWRITE|PTEVALID;
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