sdnvme: NVMe controller driver (work in progress)
basic NVMe controller driver, reads and writes work. "namespaces" show up as logical units. uses pin/msi interrupts (no msi-x support yet). one submission queue per cpu, shared completion queue. no recovery from fatal controller errors. only tested in qemu (no hardware available). commiting this so it can be found by someone who has hardware.
This commit is contained in:
cinap_lenrek
parent
83dd98022d
commit
bfae9e08be
1 changed files with 663 additions and 0 deletions
663
sys/src/9/pc/sdnvme.c
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663
sys/src/9/pc/sdnvme.c
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@ -0,0 +1,663 @@
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/error.h"
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#include "../port/sd.h"
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typedef struct WS WS;
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typedef struct CQ CQ;
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typedef struct SQ SQ;
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typedef struct Ctlr Ctlr;
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struct WS
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{
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u32int cdw0;
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ushort status;
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Rendez *sleep;
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WS **link;
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SQ *queue;
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};
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struct CQ
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{
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u32int head;
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u32int mask;
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u32int shift;
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u32int *base;
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Ctlr *ctlr;
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};
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struct SQ
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{
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u32int tail;
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u32int mask;
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u32int shift;
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u32int *base;
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WS **wait;
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Ctlr *ctlr;
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};
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struct Ctlr
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{
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QLock;
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Lock intr;
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u32int ints;
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u32int irqc[2];
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Pcidev *pci;
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u32int *reg;
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u64int cap;
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uchar *ident;
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u32int *nsid;
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int nnsid;
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u32int mps; /* mps = 1<<mpsshift */
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u32int mpsshift;
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u32int dstrd;
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CQ cq[1+1];
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SQ sq[1+MAXMACH];
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Ctlr *next;
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};
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/* controller registers */
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enum {
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Cap0,
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Cap1,
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Ver,
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IntMs,
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IntMc,
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CCfg,
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CSts = 0x1C/4,
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Nssr,
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AQAttr,
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ASQBase0,
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ASQBase1,
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ACQBase0,
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ACQBase1,
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DBell = 0x1000/4,
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};
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static u32int*
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qcmd(WS *ws, Ctlr *ctlr, int adm, u32int opc, u32int nsid, void *mptr, void *data, ulong len)
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{
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u32int cid, *e;
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u64int pa;
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SQ *sq;
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if(!adm){
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Retry:
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splhi();
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sq = &ctlr->sq[1+m->machno];
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} else {
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qlock(ctlr);
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sq = &ctlr->sq[0];
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}
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ws->sleep = &up->sleep;
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ws->queue = sq;
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ws->link = &sq->wait[sq->tail & sq->mask];
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while(*ws->link != nil){
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sched();
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if(!adm){
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/* should be very rare */
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goto Retry;
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}
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}
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*ws->link = ws;
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e = &sq->base[((cid = sq->tail++) & sq->mask)<<4];
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e[0] = opc | cid<<16;
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e[1] = nsid;
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e[2] = 0;
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e[3] = 0;
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if(mptr != nil){
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pa = PADDR(mptr);
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e[4] = pa;
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e[5] = pa>>32;
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} else {
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e[4] = 0;
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e[5] = 0;
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}
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if(len > 0){
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pa = PADDR(data);
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e[6] = pa;
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e[7] = pa>>32;
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if(len > ctlr->mps - (pa & ctlr->mps-1))
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pa += ctlr->mps - (pa & ctlr->mps-1);
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else
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pa = 0;
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} else {
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e[6] = 0;
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e[7] = 0;
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pa = 0;
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}
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e[8] = pa;
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e[9] = pa>>32;
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return e;
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}
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static void
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nvmeintr(Ureg *, void *arg)
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{
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u32int phaseshift, *e;
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WS *ws, **wp;
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Ctlr *ctlr;
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SQ *sq;
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CQ *cq;
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ctlr = arg;
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if(ctlr->ints == 0)
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return;
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ilock(&ctlr->intr);
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ctlr->reg[IntMs] = ctlr->ints;
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for(cq = &ctlr->cq[nelem(ctlr->cq)-1]; cq >= ctlr->cq; cq--){
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if(cq->base == nil)
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continue;
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phaseshift = 16 - cq->shift;
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for(;; cq->head++){
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e = &cq->base[(cq->head & cq->mask)<<2];
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if(((e[3] ^ (cq->head << phaseshift)) & 0x10000) == 0)
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break;
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if(0) iprint("nvmeintr: cq%d [%.4ux] %.8ux %.8ux %.8ux %.8ux\n",
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(int)(cq - ctlr->cq), cq->head & cq->mask,
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e[0], e[1], e[2], e[3]);
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sq = &ctlr->sq[e[2] >> 16];
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wp = &sq->wait[e[3] & sq->mask];
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if((ws = *wp) != nil && ws->link == wp){
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Rendez *z = ws->sleep;
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ws->cdw0 = e[0];
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ws->status = e[3]>>17;
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*wp = nil;
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wakeup(z);
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}
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}
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ctlr->reg[DBell + ((cq-ctlr->cq)*2+1 << ctlr->dstrd)] = cq->head & cq->mask;
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}
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if((ctlr->reg[CSts] & 3) != 1)
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iprint("nvmeintr: fatal controller error\n");
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ctlr->reg[IntMc] = ctlr->ints;
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iunlock(&ctlr->intr);
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}
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static int
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wdone(void *arg)
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{
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WS *ws = arg;
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return *ws->link != ws;
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}
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static u32int
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wcmd(WS *ws)
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{
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SQ *sq = ws->queue;
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Ctlr *ctlr = sq->ctlr;
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coherence();
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ctlr->reg[DBell + ((sq-ctlr->sq)*2+0 << ctlr->dstrd)] = sq->tail & sq->mask;
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if(sq > ctlr->sq) {
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assert(sq == &ctlr->sq[1+m->machno]);
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spllo();
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} else
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qunlock(sq->ctlr);
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while(waserror())
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;
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tsleep(ws->sleep, wdone, ws, 5);
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while(!wdone(ws)){
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nvmeintr(nil, ctlr);
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tsleep(ws->sleep, wdone, ws, 10);
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}
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poperror();
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return ws->status;
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}
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void
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checkstatus(u32int status, char *info)
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{
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if(status == 0)
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return;
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snprint(up->genbuf, sizeof(up->genbuf), "%s: status %ux", info, status);
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error(up->genbuf);
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}
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static long
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nvmebio(SDunit *u, int lun, int write, void *a, long count, uvlong lba)
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{
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u32int nsid, s, n, m, *e;
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Ctlr *ctlr;
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uchar *p;
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WS ws;
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USED(lun);
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ctlr = u->dev->ctlr;
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nsid = ctlr->nsid[u->subno];
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s = u->secsize;
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p = a;
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while(count > 0){
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m = (2*ctlr->mps - ((uintptr)p & ctlr->mps-1)) / s;
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if((n = count) > m)
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n = m;
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e = qcmd(&ws, ctlr, 0, write ? 0x01 : 0x02, nsid, nil, p, n*s);
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e[10] = lba;
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e[11] = lba>>32;
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e[12] = n-1;
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e[13] = (count>n)<<6; /* sequential request */
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e[14] = 0;
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e[15] = 0;
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checkstatus(wcmd(&ws), write ? "write" : "read");
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p += n*s;
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count -= n;
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lba += n;
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}
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return p - (uchar*)a;
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}
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static int
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nvmerio(SDreq *r)
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{
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int i, count, rw;
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uvlong lba;
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SDunit *u;
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u = r->unit;
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if(r->cmd[0] == 0x35 || r->cmd[0] == 0x91)
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return sdsetsense(r, SDok, 0, 0, 0);
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if((i = sdfakescsi(r)) != SDnostatus)
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return r->status = i;
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if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
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return i;
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r->rlen = nvmebio(u, r->lun, rw == SDwrite, r->data, count, lba);
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return r->status = SDok;
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}
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static int
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nvmeverify(SDunit *u)
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{
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Ctlr *ctlr = u->dev->ctlr;
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return u->subno < ctlr->nnsid;
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}
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static int
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nvmeonline(SDunit *u)
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{
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u32int *e, lbaf;
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uchar *info, *p;
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Ctlr *ctlr;
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WS ws;
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if(u->sectors != 0)
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return 1;
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ctlr = u->dev->ctlr;
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if((info = mallocalign(0x1000, ctlr->mps, 0, 0)) == nil)
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return 0;
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e = qcmd(&ws, ctlr, 1, 0x06, ctlr->nsid[u->subno], nil, info, 0x1000);
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e[10] = 0; // identify namespace
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if(wcmd(&ws) != 0){
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free(info);
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return 0;
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}
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p = info;
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u->sectors = p[0] | p[1]<<8 | p[2]<<16 | p[3]<<24
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| (u64int)p[4]<<32
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| (u64int)p[5]<<40
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| (u64int)p[6]<<48
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| (u64int)p[7]<<56;
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p = &info[128 + 4*(info[26]&15)];
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lbaf = p[0] | p[1]<<8 | p[2]<<16 | p[3]<<24;
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u->secsize = 1<<((lbaf>>16)&0xFF);
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free(info);
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memset(u->inquiry, 0, sizeof u->inquiry);
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u->inquiry[2] = 2;
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u->inquiry[3] = 2;
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u->inquiry[4] = sizeof u->inquiry - 4;
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memmove(u->inquiry+8, ctlr->ident+24, 20);
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return 2;
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}
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static int
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nvmerctl(SDunit *u, char *p, int l)
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{
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Ctlr *ctlr;
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char *e, *s;
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if((ctlr = u->dev->ctlr) == nil || ctlr->ident == nil)
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return 0;
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e = p+l;
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s = p;
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p = seprint(p, e, "model\t%.20s\n", (char*)ctlr->ident+24);
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p = seprint(p, e, "serial\t%.10s\n", (char*)ctlr->ident+4);
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p = seprint(p, e, "firm\t%.6s\n", (char*)ctlr->ident+64);
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p = seprint(p, e, "geometry %llud %lud\n", u->sectors, u->secsize);
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return p-s;
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}
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static void*
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cqalloc(Ctlr *ctlr, CQ *cq, u32int lgsize)
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{
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cq->ctlr = ctlr;
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cq->head = 0;
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cq->shift = lgsize-4;
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cq->mask = (1<<cq->shift)-1;
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if((cq->base = mallocalign(1<<lgsize, ctlr->mps, 0, 0)) == nil)
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error(Enomem);
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memset(cq->base, 0, 1<<lgsize);
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return cq->base;
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}
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static void*
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sqalloc(Ctlr *ctlr, SQ *sq, u32int lgsize)
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{
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sq->ctlr = ctlr;
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sq->tail = 0;
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sq->shift = lgsize-6;
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sq->mask = (1<<sq->shift)-1;
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if((sq->base = mallocalign(1<<lgsize, ctlr->mps, 0, 0)) == nil)
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error(Enomem);
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if((sq->wait = mallocz(sizeof(WS*)*(sq->mask+1), 1)) == nil)
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error(Enomem);
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memset(sq->base, 0, 1<<lgsize);
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return sq->base;
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}
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static void
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setupqueues(Ctlr *ctlr)
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{
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u32int lgsize, *e;
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CQ *cq;
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SQ *sq;
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WS ws;
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int i;
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/* Overkill */
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lgsize = 12-6+4;
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while(lgsize < 16+4 && lgsize < ctlr->mpsshift && 1<<lgsize < conf.nmach<<12-6+4)
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lgsize++;
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/* CQID1: shared completion queue */
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cq = &ctlr->cq[1];
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cqalloc(ctlr, cq, lgsize);
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e = qcmd(&ws, ctlr, 1, 0x05, ~0, nil, cq->base, 1<<lgsize);
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e[10] = (cq - ctlr->cq) | cq->mask<<16;
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e[11] = 3; /* IEN | PC */
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checkstatus(wcmd(&ws), "create completion queue");
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/* SQID[1..nmach]: submission queue per cpu */
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for(i=1; i<=conf.nmach; i++){
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sq = &ctlr->sq[i];
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sqalloc(ctlr, sq, 12);
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e = qcmd(&ws, ctlr, 1, 0x01, ~0, nil, sq->base, 0x1000);
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e[10] = i | sq->mask<<16;
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e[11] = (cq - ctlr->cq)<<16 | 1; /* CQID<<16 | PC */
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checkstatus(wcmd(&ws), "create submission queue");
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}
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ilock(&ctlr->intr);
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ctlr->ints |= 1<<(cq - ctlr->cq);
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ctlr->reg[IntMc] = ctlr->ints;
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iunlock(&ctlr->intr);
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}
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static void
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identify(Ctlr *ctlr)
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{
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u32int *e;
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WS ws;
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if(ctlr->ident == nil)
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if((ctlr->ident = mallocalign(0x1000, ctlr->mps, 0, 0)) == nil)
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error(Enomem);
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if(ctlr->nsid == nil)
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if((ctlr->nsid = mallocalign(0x1000, ctlr->mps, 0, 0)) == nil)
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error(Enomem);
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e = qcmd(&ws, ctlr, 1, 0x06, ~0, nil, ctlr->ident, 0x1000);
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e[10] = 1; // identify controller
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checkstatus(wcmd(&ws), "identify controller");
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e = qcmd(&ws, ctlr, 1, 0x06, 0, nil, ctlr->nsid, 0x1000);
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e[10] = 2; // namespace list
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checkstatus(wcmd(&ws), "namespace list");
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ctlr->nnsid = 0;
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while(ctlr->nnsid < 1024 && ctlr->nsid[ctlr->nnsid] != 0)
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ctlr->nnsid++;
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}
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static int
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nvmedisable(SDev *sd)
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{
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char name[32];
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Ctlr *ctlr;
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int i;
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ctlr = sd->ctlr;
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/* mask interrupts */
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ilock(&ctlr->intr);
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ctlr->ints = 0;
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ctlr->reg[IntMs] = ~ctlr->ints;
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iunlock(&ctlr->intr);
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/* disable controller */
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ctlr->reg[CCfg] = 0;
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for(i = 0; i < 10; i++){
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if((ctlr->reg[CSts] & 1) == 0)
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break;
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tsleep(&up->sleep, return0, nil, 100);
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}
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snprint(name, sizeof(name), "%s (%s)", sd->name, sd->ifc->name);
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intrdisable(ctlr->pci->intl, nvmeintr, ctlr, ctlr->pci->tbdf, name);
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pciclrbme(ctlr->pci); /* dma disable */
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for(i=0; i<nelem(ctlr->sq); i++){
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free(ctlr->sq[i].base);
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free(ctlr->sq[i].wait);
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}
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for(i=0; i<nelem(ctlr->cq); i++)
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free(ctlr->cq[i].base);
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|
||||
memset(ctlr->sq, 0, sizeof(ctlr->sq));
|
||||
memset(ctlr->cq, 0, sizeof(ctlr->cq));
|
||||
|
||||
free(ctlr->ident);
|
||||
ctlr->ident = nil;
|
||||
free(ctlr->nsid);
|
||||
ctlr->nsid = nil;
|
||||
ctlr->nnsid = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
nvmeenable(SDev *sd)
|
||||
{
|
||||
char name[32];
|
||||
Ctlr *ctlr;
|
||||
u64int pa;
|
||||
int to;
|
||||
|
||||
ctlr = sd->ctlr;
|
||||
|
||||
snprint(name, sizeof(name), "%s (%s)", sd->name, sd->ifc->name);
|
||||
intrenable(ctlr->pci->intl, nvmeintr, ctlr, ctlr->pci->tbdf, name);
|
||||
|
||||
if(waserror()){
|
||||
print("%s: %s\n", name, up->errstr);
|
||||
nvmedisable(sd);
|
||||
sd->nunit = 0; /* hack: prevent further probing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
pa = PADDR(cqalloc(ctlr, &ctlr->cq[0], ctlr->mpsshift));
|
||||
ctlr->reg[ACQBase0] = pa;
|
||||
ctlr->reg[ACQBase1] = pa>>32;
|
||||
|
||||
pa = PADDR(sqalloc(ctlr, &ctlr->sq[0], ctlr->mpsshift));
|
||||
ctlr->reg[ASQBase0] = pa;
|
||||
ctlr->reg[ASQBase1] = pa>>32;
|
||||
|
||||
ctlr->reg[AQAttr] = ctlr->sq[0].mask | ctlr->cq[0].mask<<16;
|
||||
|
||||
/* dma enable */
|
||||
pcisetbme(ctlr->pci);
|
||||
|
||||
/* enable interrupt */
|
||||
ilock(&ctlr->intr);
|
||||
ctlr->ints = 1;
|
||||
ctlr->reg[IntMc] = ctlr->ints;
|
||||
iunlock(&ctlr->intr);
|
||||
|
||||
/* enable controller */
|
||||
ctlr->reg[CCfg] = 1 | (ctlr->mpsshift-12)<<7 | 6<<16 | 4<<20;
|
||||
|
||||
for(to = (ctlr->cap>>24) & 255; to >= 0; to--){
|
||||
tsleep(&up->sleep, return0, nil, 500);
|
||||
if((ctlr->reg[CSts] & 3) == 1)
|
||||
goto Ready;
|
||||
}
|
||||
if(ctlr->reg[CSts] & 2)
|
||||
error("fatal controller status during initialization");
|
||||
error("controller initialization timeout");
|
||||
Ready:
|
||||
identify(ctlr);
|
||||
setupqueues(ctlr);
|
||||
|
||||
poperror();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static Ctlr*
|
||||
nvmepnpctlrs(void)
|
||||
{
|
||||
Ctlr *ctlr, *h, *t;
|
||||
Pcidev *p;
|
||||
int i;
|
||||
|
||||
h = t = nil;
|
||||
for(p = nil; p = pcimatch(p, 0, 0);){
|
||||
if(p->ccrb != 1 || p->ccru != 8 || p->ccrp != 2)
|
||||
continue;
|
||||
if(p->mem[0].size == 0)
|
||||
continue;
|
||||
if((ctlr = malloc(sizeof(*ctlr))) == nil){
|
||||
print("nvme: no memory for Ctlr\n");
|
||||
break;
|
||||
}
|
||||
ctlr->pci = p;
|
||||
ctlr->reg = vmap(p->mem[0].bar & ~0xF, p->mem[0].size);
|
||||
if(ctlr->reg == nil){
|
||||
print("nvme: can't vmap bar0\n");
|
||||
Bad:
|
||||
if(ctlr->reg != nil)
|
||||
vunmap(ctlr->reg, p->mem[0].size);
|
||||
free(ctlr);
|
||||
continue;
|
||||
}
|
||||
ctlr->cap = ctlr->reg[Cap0];
|
||||
ctlr->cap |= (u64int)ctlr->reg[Cap1]<<32;
|
||||
|
||||
/* mask interrupts */
|
||||
ctlr->ints = 0;
|
||||
ctlr->reg[IntMs] = ~ctlr->ints;
|
||||
|
||||
/* disable controller */
|
||||
ctlr->reg[CCfg] = 0;
|
||||
|
||||
if((ctlr->cap&(1ULL<<37)) == 0){
|
||||
print("nvme: doesnt support NVM commactlr set: %ux\n",
|
||||
(u32int)(ctlr->cap>>37) & 0xFF);
|
||||
goto Bad;
|
||||
}
|
||||
|
||||
/* use 64K page size when possible */
|
||||
ctlr->dstrd = (ctlr->cap >> 32) & 15;
|
||||
for(i = (ctlr->cap >> 48) & 15; i < ((ctlr->cap >> 52) & 15); i++){
|
||||
if(i >= 16-12) /* 64K */
|
||||
break;
|
||||
}
|
||||
ctlr->mpsshift = i+12;
|
||||
ctlr->mps = 1 << ctlr->mpsshift;
|
||||
|
||||
if(h == nil)
|
||||
h = ctlr;
|
||||
else
|
||||
t->next = ctlr;
|
||||
t = ctlr;
|
||||
}
|
||||
|
||||
return h;
|
||||
}
|
||||
|
||||
SDifc sdnvmeifc;
|
||||
|
||||
static SDev*
|
||||
nvmepnp(void)
|
||||
{
|
||||
SDev *s, *h, *t;
|
||||
Ctlr *ctlr;
|
||||
int id;
|
||||
|
||||
h = t = nil;
|
||||
|
||||
id = 'N';
|
||||
for(ctlr = nvmepnpctlrs(); ctlr != nil; ctlr = ctlr->next){
|
||||
if((s = malloc(sizeof(*s))) == nil)
|
||||
break;
|
||||
s->ctlr = ctlr;
|
||||
s->idno = id++;
|
||||
s->ifc = &sdnvmeifc;
|
||||
s->nunit = 1024;
|
||||
if(h)
|
||||
t->next = s;
|
||||
else
|
||||
h = s;
|
||||
t = s;
|
||||
}
|
||||
|
||||
return h;
|
||||
}
|
||||
|
||||
SDifc sdnvmeifc = {
|
||||
"nvme", /* name */
|
||||
|
||||
nvmepnp, /* pnp */
|
||||
nil, /* legacy */
|
||||
nvmeenable, /* enable */
|
||||
nvmedisable, /* disable */
|
||||
|
||||
nvmeverify, /* verify */
|
||||
nvmeonline, /* online */
|
||||
nvmerio, /* rio */
|
||||
nvmerctl, /* rctl */
|
||||
nil, /* wctl */
|
||||
|
||||
nvmebio, /* bio */
|
||||
nil, /* probe */
|
||||
nil, /* clear */
|
||||
nil, /* rtopctl */
|
||||
nil, /* wtopctl */
|
||||
};
|
||||
Loading…
Reference in a new issue