From bd23963c8f359d0a3c802f7cd96b51b4d36b01ac Mon Sep 17 00:00:00 2001
From: cinap_lenrek <cinap_lenrek@felloff.net>
Date: Thu, 2 Jul 2020 21:04:01 +0200
Subject: [PATCH] bcm64: fix usb xhci controller on pi4 8GB variant (thanks
 richard miller)

On the 8GB variant of the raspberry pi 4,
the eeprom chip for the xhci controller is missing and
instead loaded from sdram (by the gpu firmware).

for this, the gpu firmware needs to be notified of
the xhci controllers pci bus address (after reset)
that was assigned by our pci enumeration code.
---
 sys/src/9/bcm/vcore.c      | 17 +++++++++++++++++
 sys/src/9/bcm64/archbcm4.c | 13 +++++++++++++
 sys/src/9/bcm64/fns.h      |  1 +
 sys/src/9/bcm64/pi4        |  4 ++--
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/sys/src/9/bcm/vcore.c b/sys/src/9/bcm/vcore.c
index 818c12a35..91cc7dcf9 100644
--- a/sys/src/9/bcm/vcore.c
+++ b/sys/src/9/bcm/vcore.c
@@ -53,6 +53,7 @@ enum {
 	TagSetEgpioConf	= 0x00038043,
 
 	TagGettemp	= 0x00030006,
+	TagXhciReset	= 0x00030058,
 	TagFballoc	= 0x00040001,
 	TagFbfree	= 0x00048001,
 	TagFbblank	= 0x00040002,
@@ -413,3 +414,19 @@ egpset(uint port, int on)
 	buf[1] = on;
 	vcreq(TagSetEgpioState, buf, sizeof(buf), sizeof(buf));
 }
+
+/*
+ * Notify gpu that xhci firmware might need loading. This is for some
+ * pi4 board versions which are missing the eeprom chip for the vl805,
+ * requiring its firmware to come from the boot eeprom instead.
+ */
+int
+xhcireset(int devaddr)
+{
+	u32int buf[1];
+
+	buf[0] = devaddr;
+	if(vcreq(TagXhciReset, buf, sizeof(buf), sizeof(buf[0])) == sizeof(buf[0]))
+		return buf[0];
+	return -1;
+}
diff --git a/sys/src/9/bcm64/archbcm4.c b/sys/src/9/bcm64/archbcm4.c
index 55e90d45a..d47ba96e1 100644
--- a/sys/src/9/bcm64/archbcm4.c
+++ b/sys/src/9/bcm64/archbcm4.c
@@ -172,5 +172,18 @@ wakecpu(uint cpu)
 void
 archbcm4link(void)
 {
+	Pcidev *p;
+
+	/*
+	 * The firmware resets PCI before starting the host OS because
+	 * without SDRAM the VL805 makes inbound requests to page-in firmware
+	 * from SDRAM. If the OS has a different PCI mapping that would all break.
+	 * There's no way to pause and move the mappings and it's not really desirable
+	 * for the firmware to dictate the PCI configuration. Consequently, the mailbox
+	 * is required so that the OS can reset the VLI after asserting PCI chip reset.
+	 */
+	if((p = pcimatch(nil, 0x1106, 0x3483)) != nil)
+		xhcireset(BUSBNO(p->tbdf)<<20 | BUSDNO(p->tbdf)<<15 | BUSFNO(p->tbdf)<<12);
+
 	// addclock0link(wdogfeed, HZ);
 }
diff --git a/sys/src/9/bcm64/fns.h b/sys/src/9/bcm64/fns.h
index 34cc0c812..f42c2736c 100644
--- a/sys/src/9/bcm64/fns.h
+++ b/sys/src/9/bcm64/fns.h
@@ -170,6 +170,7 @@ extern uint getcputemp(void);
 extern void vgpinit(void);
 extern void vgpset(uint port, int on);
 extern void egpset(uint port, int on);
+extern int xhcireset(int devaddr);
 
 /* bootargs */
 extern void bootargsinit(uintptr);
diff --git a/sys/src/9/bcm64/pi4 b/sys/src/9/bcm64/pi4
index 8d30d289d..1a3b815ff 100644
--- a/sys/src/9/bcm64/pi4
+++ b/sys/src/9/bcm64/pi4
@@ -27,11 +27,11 @@ dev
 link
 	gisb
 	pci
-	archbcm4
+	archbcm4	pci
+	usbxhci		pci archbcm4
 	ethergenet	ethermii
 	ethermedium
 	loopbackmedium
-	usbxhci		pci
 
 ip
 	tcp