pc, pc64: handle 64-bit pci membars
this avoids listing the upper half of 64-bit membars in Pcidev.mem[] array avoiding potential confusion in drivers. we also check if the upper half is programmed to zero by bios and otherwise zap the entry in Pcidev.mem[] and print a warning.
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@ -249,6 +249,7 @@ pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
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if(size == 0)
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continue;
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p->mem[i].size = size;
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if(v & 1) {
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itb->dev = p;
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itb->bar = i;
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@ -260,9 +261,10 @@ pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
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mtb->bar = i;
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mtb->siz = size;
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mtb++;
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}
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p->mem[i].size = size;
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if((v & 7) == 4)
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i++;
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}
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}
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}
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@ -438,11 +440,24 @@ pcilscan(int bno, Pcidev** list, Pcidev *parent)
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case 0x0C: /* serial bus controllers */
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if((hdt & 0x7F) != 0)
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break;
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rno = PciBAR0 - 4;
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rno = PciBAR0;
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for(i = 0; i < nelem(p->mem); i++) {
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rno += 4;
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p->mem[i].bar = pcicfgr32(p, rno);
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p->mem[i].size = pcibarsize(p, rno);
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if((p->mem[i].bar & 7) == 4){
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ulong hi;
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rno += 4;
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hi = pcicfgr32(p, rno);
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if(hi != 0){
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print("ignoring 64-bit bar %d: %llux %d from %T\n",
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i, (uvlong)hi<<32 | p->mem[i].bar, p->mem[i].size, p->tbdf);
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p->mem[i].bar = 0;
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p->mem[i].size = 0;
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}
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i++;
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}
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rno += 4;
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}
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break;
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