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5a: assemble constant >>0 right shifts as <<0 (no shift), allow >>32

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previously, right shift >>0 resulted in >>32 being emited. this
is especially problematic when the shift count comes from a macro
expansion.

we now handle constant shift >>0 as <<0 (no shift) and allow
shift by 32 be specified.

this applies to logical right shift (>>) arithmetic right shift (->)
and right rotate (@>).
This commit is contained in:
cinap_lenrek 2016-09-03 17:11:38 +02:00
parent 607f3bc55c
commit b46a0e97ea
1 changed files with 14 additions and 7 deletions
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21
sys/src/cmd/5a/a.y
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@ -469,27 +469,34 @@ regreg:
shift: shift:
spreg '<' '<' rcon spreg '<' '<' rcon
{ {
nullshift:
$$ = nullgen; $$ = nullgen;
$$.type = D_SHIFT; $$.type = D_SHIFT;
$$.offset = $1 | $4 | (0 << 5); $$.offset = $1 | ($4 & ~(32<<7)) | (0 << 5);
} }
| spreg '>' '>' rcon | spreg '>' '>' rcon
{ {
if($4 == 0)
goto nullshift;
$$ = nullgen; $$ = nullgen;
$$.type = D_SHIFT; $$.type = D_SHIFT;
$$.offset = $1 | $4 | (1 << 5); $$.offset = $1 | ($4 & ~(32<<7)) | (1 << 5);
} }
| spreg '-' '>' rcon | spreg '-' '>' rcon
{ {
if($4 == 0)
goto nullshift;
$$ = nullgen; $$ = nullgen;
$$.type = D_SHIFT; $$.type = D_SHIFT;
$$.offset = $1 | $4 | (2 << 5); $$.offset = $1 | ($4 & ~(32<<7)) | (2 << 5);
} }
| spreg LAT '>' rcon | spreg LAT '>' rcon
{ {
if($4 == 0)
goto nullshift;
$$ = nullgen; $$ = nullgen;
$$.type = D_SHIFT; $$.type = D_SHIFT;
$$.offset = $1 | $4 | (3 << 5); $$.offset = $1 | ($4 & ~(32<<7)) | (3 << 5);
} }
rcon: rcon:
@ -497,13 +504,13 @@ rcon:
{ {
if($$ < 0 || $$ >= 16) if($$ < 0 || $$ >= 16)
print("register value out of range\n"); print("register value out of range\n");
$$ = (($1&15) << 8) | (1 << 4); $$ = ($1 << 8) | (1 << 4);
} }
| con | con
{ {
if($$ < 0 || $$ >= 32) if($$ < 0 || $$ > 32)
print("shift value out of range\n"); print("shift value out of range\n");
$$ = ($1&31) << 7; $$ = ($1 << 7);
} }
sreg: sreg: