imx8: add i2c bus driver
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cinap_lenrek
parent
476e7341d5
commit
a23e9ac65d
270
sys/src/9/imx8/i2cimx.c
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270
sys/src/9/imx8/i2cimx.c
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@ -0,0 +1,270 @@
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/i2c.h"
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enum {
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Moduleclk = 25*Mhz,
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I2C_IADR = 0x00,
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I2C_IFDR = 0x04,
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I2C_I2CR = 0x08,
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I2CR_IEN = 1<<7,
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I2CR_IIEN = 1<<6,
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I2CR_MSTA = 1<<5,
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I2CR_MTX = 1<<4,
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I2CR_TXAK = 1<<3,
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I2CR_RSTA = 1<<2,
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I2C_I2SR = 0x0C,
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I2SR_ICF = 1<<7,
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I2SR_IAAS = 1<<6,
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I2SR_IBB = 1<<5,
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I2SR_IAL = 1<<4,
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I2SR_SRW = 1<<2,
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I2SR_IIF = 1<<1,
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I2SR_RXAK = 1<<0,
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I2C_I2DR = 0x10,
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};
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typedef struct Ctlr Ctlr;
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struct Ctlr
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{
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void *regs;
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int irq;
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Rendez;
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};
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static void
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interrupt(Ureg*, void *arg)
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{
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I2Cbus *bus = arg;
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Ctlr *ctlr = bus->ctlr;
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wakeup(ctlr);
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}
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static int
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haveirq(void *arg)
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{
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uchar *regs = arg;
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return regs[I2C_I2SR] & (I2SR_IAL|I2SR_IIF);
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}
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static int
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waitsr(Ctlr *ctlr, int inv, int mask)
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{
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uchar *regs = ctlr->regs;
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int sr;
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for(;;){
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sr = regs[I2C_I2SR];
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if(sr & I2SR_IAL){
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regs[I2C_I2SR] = sr & ~(I2SR_IAL|I2SR_IIF);
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break;
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}
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if(sr & I2SR_IIF)
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regs[I2C_I2SR] = sr & ~I2SR_IIF;
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if((sr ^ inv) & mask)
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break;
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/* polling mode */
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if(up == nil || !islo())
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continue;
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tsleep(ctlr, haveirq, regs, 1);
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}
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return sr ^ inv;
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}
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static uchar dummy;
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static int
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io(I2Cbus *bus, uchar *pkt, int olen, int ilen)
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{
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Ctlr *ctlr = bus->ctlr;
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uchar *regs = ctlr->regs;
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int cr, sr, alen, o, i;
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cr = regs[I2C_I2CR];
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if((cr & I2CR_IEN) == 0)
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return -1;
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o = 0;
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if(olen <= 0)
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goto Stop;
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alen = 1;
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if((pkt[0] & 0xF8) == 0xF0 && olen > alen)
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alen++;
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regs[I2C_IADR] = (pkt[0]&0xFE)^0xFE; /* make sure doesnt match */
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/* wait for bus idle */
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waitsr(ctlr, I2SR_IBB, I2SR_IBB);
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/* start */
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cr |= I2CR_MSTA | I2CR_MTX | I2CR_TXAK | I2CR_IIEN;
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regs[I2C_I2CR] = cr;
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/* wait for bus busy */
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if(waitsr(ctlr, 0, I2SR_IBB) & I2SR_IAL)
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goto Err;
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if(olen > alen)
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pkt[0] &= ~1;
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for(o=0; o<olen; o++){
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regs[I2C_I2DR] = pkt[o];
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sr = waitsr(ctlr, 0, I2SR_IIF);
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if(sr & I2SR_IAL)
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goto Err;
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if(sr & I2SR_RXAK)
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goto Stop;
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}
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if(ilen <= 0)
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goto Stop;
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if((pkt[0]&1) == 0){
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regs[I2C_I2CR] = cr | I2CR_RSTA;
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pkt[0] |= 1;
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for(i=0; i<alen; i++){
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regs[I2C_I2DR] = pkt[i];
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sr = waitsr(ctlr, 0, I2SR_IIF);
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if(sr & I2SR_IAL)
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goto Err;
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if(sr & I2SR_RXAK)
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goto Stop;
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}
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}
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cr &= ~(I2CR_MTX | I2CR_TXAK);
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if(ilen == 1) cr |= I2CR_TXAK;
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regs[I2C_I2CR] = cr;
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dummy = regs[I2C_I2DR]; /* start the next read */
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for(i=1; i<=ilen; i++){
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sr = waitsr(ctlr, I2SR_ICF, I2SR_IIF);
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if(sr & I2SR_IAL)
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goto Err;
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if(sr & I2SR_ICF)
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goto Stop;
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if(i == ilen){
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cr &= ~(I2CR_MSTA|I2CR_IIEN);
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regs[I2C_I2CR] = cr;
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}
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else if(i == ilen-1){
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cr |= I2CR_TXAK;
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regs[I2C_I2CR] = cr;
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}
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pkt[o++] = regs[I2C_I2DR];
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}
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return o;
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Err:
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o = -1;
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Stop:
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cr &= ~(I2CR_MTX|I2CR_MSTA|I2CR_RSTA|I2CR_IIEN);
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regs[I2C_I2CR] = cr;
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return o;
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}
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static int
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divindex(int v)
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{
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static int tab[] = {
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/* 0x00 */ 30, 32, 36, 42, 48, 52, 60, 72,
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/* 0x08 */ 80, 88, 104, 128, 144, 160, 192, 240,
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/* 0x10 */ 288, 320, 384, 480, 576, 640, 768, 960,
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/* 0x18 */1152,1280,1536,1920,2304,2560,3072,3840,
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/* 0x20 */ 22, 24, 26, 28, 32, 36, 40, 44,
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/* 0x28 */ 48, 56, 64, 72, 80, 96, 112, 128,
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/* 0x30 */ 160, 192, 224, 256, 320, 384, 448, 512,
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/* 0x38 */ 640, 768, 896,1024,1280,1536,1792,2048,
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};
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int i, x = -1;
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for(i = 0; i < nelem(tab); i++){
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if(tab[i] < v)
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continue;
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if(x < 0 || tab[i] < tab[x]){
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x = i;
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if(tab[i] == v)
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break;
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}
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}
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return x;
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}
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static void
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clkenable(char *name, int on)
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{
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char clk[32];
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snprint(clk, sizeof(clk), "%s.ipg_clk_patref", name);
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setclkgate(clk, 0);
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if(on) {
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setclkrate(clk, "osc_25m_ref_clk", Moduleclk);
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setclkgate(clk, 1);
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}
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}
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static int
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init(I2Cbus *bus)
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{
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Ctlr *ctlr = bus->ctlr;
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uchar *regs = ctlr->regs;
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clkenable(bus->name, 1);
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regs[I2C_IFDR] = divindex(Moduleclk / bus->speed);
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regs[I2C_IADR] = 0;
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regs[I2C_I2CR] = I2CR_IEN;
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delay(1);
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intrenable(ctlr->irq, interrupt, bus, BUSUNKNOWN, bus->name);
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return 0;
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}
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static Ctlr ctlr1 = {
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.regs = (void*)(VIRTIO + 0xA20000),
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.irq = IRQi2c1,
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};
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static Ctlr ctlr2 = {
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.regs = (void*)(VIRTIO + 0xA30000),
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.irq = IRQi2c2,
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};
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static Ctlr ctlr3 = {
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.regs = (void*)(VIRTIO + 0xA40000),
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.irq = IRQi2c3,
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};
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static Ctlr ctlr4 = {
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.regs = (void*)(VIRTIO + 0xA50000),
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.irq = IRQi2c4,
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};
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void
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i2cimxlink(void)
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{
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static I2Cbus i2c1 = { "i2c1", 400000, &ctlr1, init, io };
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static I2Cbus i2c3 = { "i2c3", 400000, &ctlr3, init, io };
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static I2Cbus i2c4 = { "i2c4", 400000, &ctlr4, init, io };
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iomuxpad("pad_i2c1_sda", "i2c1_sda", "SION ~LVTTL ~HYS PUE ODE MAX 40_OHM");
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iomuxpad("pad_i2c1_scl", "i2c1_scl", "SION ~LVTTL ~HYS PUE ODE MAX 40_OHM");
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addi2cbus(&i2c1);
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iomuxpad("pad_i2c3_sda", "i2c3_sda", "SION ~LVTTL ~HYS PUE ODE MAX 40_OHM");
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iomuxpad("pad_i2c3_scl", "i2c3_scl", "SION ~LVTTL ~HYS PUE ODE MAX 40_OHM VSEL_0");
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addi2cbus(&i2c3);
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iomuxpad("pad_i2c4_sda", "i2c4_sda", "SION ~LVTTL ~HYS PUE ODE MAX 40_OHM");
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iomuxpad("pad_i2c4_scl", "i2c4_scl", "SION ~LVTTL ~HYS PUE ODE MAX 40_OHM");
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addi2cbus(&i2c4);
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}
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