igfx: vga support on x230, fix fdi link setup, LG Flatron L1730P vgadb entry
This commit is contained in:
cinap_lenrek
parent
773f1c5f6a
commit
9b28b2d97b
2 changed files with 198 additions and 84 deletions
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@ -1707,3 +1707,12 @@ x200s=1280x800 # 60Hz
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vrs=802 vre=804 vt=830
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hsync=- vsync=-
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lcd=1
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#
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# LG Flatron L1730P
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#
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l1730p=1280x1024 # 60Hz
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clock=108
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shb=1320 ehb=1440 ht=1688
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vrs=1025 vre=1028 vt=1066
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hsync=+ vsync=+
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@ -16,6 +16,7 @@ typedef struct Curs Curs;
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typedef struct Plane Plane;
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typedef struct Trans Trans;
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typedef struct Pipe Pipe;
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typedef struct Igfx Igfx;
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enum {
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MHz = 1000000,
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@ -114,7 +115,6 @@ struct Pipe {
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Pfit *pfit; /* selected panel fitter */
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};
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typedef struct Igfx Igfx;
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struct Igfx {
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Ctlr *ctlr;
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Pcidev *pci;
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@ -151,9 +151,11 @@ struct Igfx {
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/* common */
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Reg adpa;
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Reg lvds;
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Edid *lvdsedid;
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Reg vgacntrl;
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Edid *adpaedid;
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Edid *lvdsedid;
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};
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static u32int
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@ -309,7 +311,7 @@ devtype(Igfx *igfx)
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return -1;
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}
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static void snarfedid(Igfx*);
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static Edid* snarfedid(Igfx*, int port, int addr);
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static void
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snarf(Vga* vga, Ctlr* ctlr)
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@ -370,6 +372,9 @@ snarf(Vga* vga, Ctlr* ctlr)
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if(igfx->pipe[y].pfit == nil)
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igfx->pipe[y].pfit = &igfx->pfit[0];
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igfx->ppstatus = snarfreg(igfx, 0x61200);
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igfx->ppcontrol = snarfreg(igfx, 0x61204);
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igfx->vgacntrl = snarfreg(igfx, 0x071400);
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break;
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@ -389,7 +394,7 @@ snarf(Vga* vga, Ctlr* ctlr)
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igfx->rawclkfreq = snarfreg(igfx, 0xC6204);
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igfx->ssc4params = snarfreg(igfx, 0xC6210);
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/* cpu displayport A*/
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/* cpu displayport A */
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igfx->dp[0].ctl = snarfreg(igfx, 0x64000);
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igfx->dp[0].auxctl = snarfreg(igfx, 0x64010);
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igfx->dp[0].auxdat[0] = snarfreg(igfx, 0x64014);
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@ -454,7 +459,8 @@ snarf(Vga* vga, Ctlr* ctlr)
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for(x=0; x<igfx->npipe; x++)
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snarfpipe(igfx, x);
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snarfedid(igfx);
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igfx->adpaedid = snarfedid(igfx, 2, 0x50);
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igfx->lvdsedid = snarfedid(igfx, 3, 0x50);
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ctlr->flag |= Fsnarf;
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}
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@ -476,13 +482,16 @@ genpll(int freq, int cref, int P2, int *m1, int *m2, int *n, int *p1)
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best = -1;
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for(N=3; N<=8; N++)
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for(M2=5; M2<=9; M2++)
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for(M1=10; M1<=20; M1++){
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// for(M1=10; M1<=20; M1++){
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for(M1=12; M1<=22; M1++){
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M = 5*(M1+2) + (M2+2);
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if(M < 70 || M > 120)
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if(M < 79 || M > 127)
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// if(M < 70 || M > 120)
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continue;
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for(P1=1; P1<=8; P1++){
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P = P1 * P2;
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if(P < 4 || P > 98)
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if(P < 5 || P > 98)
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// if(P < 4 || P > 98)
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continue;
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a = cref;
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a *= M;
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@ -506,6 +515,20 @@ genpll(int freq, int cref, int P2, int *m1, int *m2, int *n, int *p1)
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return best;
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}
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static int
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getcref(Igfx *igfx, int x)
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{
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Dpll *dpll;
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dpll = &igfx->dpll[x];
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if(igfx->type == TypeG45){
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if(((dpll->ctrl.v >> 13) & 3) == 3)
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return 100*MHz;
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return 96*MHz;
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}
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return 120*MHz;
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}
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static int
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initdpll(Igfx *igfx, int x, int freq, int islvds, int ishdmi)
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{
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@ -517,22 +540,27 @@ initdpll(Igfx *igfx, int x, int freq, int islvds, int ishdmi)
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/* PLL Reference Input Select */
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dpll = igfx->pipe[x].dpll;
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dpll->ctrl.v &= ~(3<<13);
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dpll->ctrl.v |= (islvds ? 2 : 0) << 13;
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cref = islvds ? 100*MHz : 96*MHz;
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dpll->ctrl.v |= (islvds ? 3 : 0) << 13;
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break;
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case TypeIVB:
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/* transcoder dpll enable */
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igfx->dpllsel.v |= 8<<(x*4);
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/* program rawclock to 125MHz */
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igfx->rawclkfreq.v = 125;
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if(islvds){
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/* 120MHz SSC integrated source enable */
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igfx->drefctl.v &= ~(3<<11);
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igfx->drefctl.v |= 2<<11;
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/* 120MHz SSC4 modulation en */
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igfx->drefctl.v |= 2;
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igfx->drefctl.v &= ~(3<<13);
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igfx->drefctl.v &= ~(3<<11);
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igfx->drefctl.v &= ~(3<<9);
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igfx->drefctl.v &= ~(3<<7);
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igfx->drefctl.v &= ~3;
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if(islvds){
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igfx->drefctl.v |= 2<<11;
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igfx->drefctl.v |= 1;
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} else {
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igfx->drefctl.v |= 2<<9;
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}
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/*
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* PLL Reference Input Select:
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* 000 DREFCLK (default is 120 MHz) for DAC/HDMI/DVI/DP
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@ -542,11 +570,11 @@ initdpll(Igfx *igfx, int x, int freq, int islvds, int ishdmi)
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dpll = igfx->pipe[x].fdi->dpll;
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dpll->ctrl.v &= ~(7<<13);
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dpll->ctrl.v |= (islvds ? 3 : 0) << 13;
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cref = 120*MHz;
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break;
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default:
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return -1;
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}
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cref = getcref(igfx, x);
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/* Dpll Mode select */
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dpll->ctrl.v &= ~(3<<26);
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@ -603,11 +631,13 @@ initdatalinkmn(Trans *t, int freq, int lsclk, int lanes, int tu, int bpp)
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n = 0x800000;
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m = (n * ((freq * bpp)/8)) / (lsclk * lanes);
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t->dm[0].v = (tu-1)<<25 | m;
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t->dn[0].v = n;
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n = 0x80000;
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m = (n * freq) / lsclk;
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t->lm[0].v = m;
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t->ln[0].v = n;
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@ -628,11 +658,13 @@ inittrans(Trans *t, Mode *m)
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/* trans/pipe timing */
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t->ht.v = (m->ht - 1)<<16 | (m->x - 1);
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t->hb.v = t->ht.v;
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t->hs.v = (m->ehb - 1)<<16 | (m->shb - 1);
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t->vt.v = (m->vt - 1)<<16 | (m->y - 1);
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t->vb.v = t->vt.v;
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t->vs.v = (m->vre - 1)<<16 | (m->vrs - 1);
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t->hb.v = t->ht.v;
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t->vb.v = t->vt.v;
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t->vss.v = 0;
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}
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@ -647,7 +679,7 @@ initpipe(Pipe *p, Mode *m)
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p->src.v = (m->x - 1)<<16 | (m->y - 1);
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if(p->pfit != nil){
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/* panel fitter enable, hardcoded coefficients */
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/* panel fitter on, hardcoded coefficients */
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p->pfit->ctrl.v = 1<<31 | 1<<23;
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p->pfit->winpos.v = 0;
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p->pfit->winsize.v = (m->x << 16) | m->y;
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@ -658,7 +690,7 @@ initpipe(Pipe *p, Mode *m)
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/* default for displayport */
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tu = 64;
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bpc = 8;
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bpc = 6; /* why */
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lanes = 1;
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fdi = p->fdi;
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@ -666,29 +698,10 @@ initpipe(Pipe *p, Mode *m)
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/* enable and set monitor timings for transcoder */
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inittrans(fdi, m);
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/*
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* hack:
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* we do not program fdi in load(), so use
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* snarfed bios initialized values for now.
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*/
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if(fdi->rxctl.v & (1<<31)){
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tu = 1+(fdi->rxtu[0].v >> 25);
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bpc = bpctab[(fdi->rxctl.v >> 16) & 3];
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lanes = 1+((fdi->rxctl.v >> 19) & 7);
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}
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/* fdi tx enable */
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fdi->txctl.v |= (1<<31);
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/* tx port width selection */
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fdi->txctl.v &= ~(7<<19);
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fdi->txctl.v |= (lanes-1)<<19;
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/* tx fdi pll enable */
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fdi->txctl.v |= (1<<14);
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/* clear auto training bits */
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fdi->txctl.v &= ~(7<<8 | 1);
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/* fdi rx enable */
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fdi->rxctl.v |= (1<<31);
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/* rx port width selection */
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fdi->rxctl.v &= ~(7<<19);
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fdi->rxctl.v |= (lanes-1)<<19;
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@ -702,10 +715,10 @@ initpipe(Pipe *p, Mode *m)
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break;
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}
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}
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/* rx fdi pll enable */
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fdi->rxctl.v |= (1<<13);
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/* rx fdi rawclk to pcdclk selection */
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fdi->rxctl.v |= (1<<4);
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/* enhanced framing on */
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fdi->rxctl.v |= (1<<6);
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fdi->txctl.v |= (1<<18);
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/* tusize 1 and 2 */
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fdi->rxtu[0].v = (tu-1)<<25;
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@ -742,7 +755,14 @@ init(Vga* vga, Ctlr* ctlr)
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/* disable vga */
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igfx->vgacntrl.v |= (1<<31);
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x = 0;
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/* disable all pipes adpa and lvds */
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igfx->ppcontrol.v &= 0xFFFF;
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igfx->ppcontrol.v &= ~5;
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igfx->lvds.v &= ~(1<<31);
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igfx->adpa.v &= ~(1<<31);
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for(x=0; x<igfx->npipe; x++)
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igfx->pipe[x].conf.v &= ~(1<<31);
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islvds = 0;
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if((val = dbattr(m->attr, "lcd")) != nil && atoi(val) != 0){
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islvds = 1;
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@ -752,14 +772,18 @@ init(Vga* vga, Ctlr* ctlr)
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else
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x = (igfx->lvds.v >> 30) & 1;
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igfx->lvds.v |= (1<<31);
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igfx->ppcontrol.v &= ~0xFFFF0000;
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igfx->ppcontrol.v |= 5;
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} else {
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if(igfx->npipe > 2)
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x = (igfx->adpa.v >> 29) & 3;
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else
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x = (igfx->adpa.v >> 30) & 1;
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igfx->adpa.v |= (1<<31);
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}
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p = &igfx->pipe[x];
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/* plane enable, 32bpp and assign pipe */
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p->dsp->cntr.v = (1<<31) | (6<<26) | (x<<24);
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/* plane enable, 32bpp */
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p->dsp->cntr.v = (1<<31) | (6<<26);
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/* stride must be 64 byte aligned */
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p->dsp->stride.v = m->x * (m->z / 8);
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@ -839,17 +863,25 @@ loadtrans(Igfx *igfx, Trans *t)
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static void
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enablepipe(Igfx *igfx, int x)
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{
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int i;
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Pipe *p;
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p = &igfx->pipe[x];
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if((p->conf.v & (1<<31)) == 0)
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return; /* pipe is disabled, done */
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if(0){
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if(p->fdi->rxctl.a != 0){
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p->fdi->rxctl.v &= ~(1<<31);
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p->fdi->rxctl.v &= ~(1<<4); /* rawclk */
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p->fdi->rxctl.v |= (1<<13); /* enable pll */
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loadreg(igfx, p->fdi->rxctl);
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sleep(5);
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p->fdi->rxctl.v |= (1<<4); /* pcdclk */
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loadreg(igfx, p->fdi->rxctl);
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sleep(5);
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p->fdi->txctl.v &= ~(7<<8 | 1); /* clear auto training bits */
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p->fdi->txctl.v &= ~(1<<31);
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p->fdi->rxctl.v |= (1<<14); /* enable pll */
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loadreg(igfx, p->fdi->txctl);
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sleep(5);
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}
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@ -879,18 +911,28 @@ enablepipe(Igfx *igfx, int x)
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loadreg(igfx, p->cur->pos);
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loadreg(igfx, p->cur->base); /* arm */
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if(0){
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if(p->fdi->rxctl.a != 0){
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/* enable fdi */
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loadreg(igfx, p->fdi->rxtu[1]);
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loadreg(igfx, p->fdi->rxtu[0]);
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loadreg(igfx, p->fdi->rxmisc);
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p->fdi->rxctl.v &= ~(3<<8 | 1<<10 | 3);
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p->fdi->rxctl.v |= (1<<31);
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p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 00 */
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p->fdi->rxctl.v |= 1<<10; /* auto train enable */
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p->fdi->rxctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->rxctl);
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p->fdi->txctl.v &= ~(3<<8 | 1<<10 | 2);
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p->fdi->txctl.v |= (1<<31);
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p->fdi->txctl.v &= ~(3<<8); /* link train pattern 00 */
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p->fdi->txctl.v |= 1<<10; /* auto train enable */
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p->fdi->txctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->txctl);
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/* wait for link training done */
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for(i=0; i<200; i++){
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sleep(5);
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if(rr(igfx, p->fdi->txctl.a) & 2)
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break;
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}
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}
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/* enable the transcoder */
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@ -902,10 +944,6 @@ disabletrans(Igfx *igfx, Trans *t)
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{
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int i;
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/* the front fell off on x230 */
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if(igfx->type == TypeIVB && t == &igfx->pipe[0])
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goto skippipe;
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/* disable transcoder / pipe */
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csr(igfx, t->conf.a, 1<<31, 0);
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for(i=0; i<100; i++){
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@ -916,7 +954,6 @@ disabletrans(Igfx *igfx, Trans *t)
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/* workarround: clear timing override bit */
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csr(igfx, t->chicken.a, 1<<31, 0);
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skippipe:
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/* disable dpll */
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if(t->dpll != nil)
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csr(igfx, t->dpll->ctrl.a, 1<<31, 0);
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@ -943,11 +980,9 @@ disablepipe(Igfx *igfx, int x)
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if(p->pfit != nil)
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csr(igfx, p->pfit->ctrl.a, 1<<31, 0);
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if(0){
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/* disable fdi transmitter and receiver */
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csr(igfx, p->fdi->txctl.a, 1<<31 | 1<<10, 0);
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csr(igfx, p->fdi->rxctl.a, 1<<31 | 1<<10, 0);
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}
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/* disable fdi transmitter and receiver */
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csr(igfx, p->fdi->txctl.a, 1<<31 | 1<<10, 0);
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csr(igfx, p->fdi->rxctl.a, 1<<31 | 1<<10, 0);
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/* disable displayport transcoder */
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csr(igfx, p->fdi->dpctl.a, 1<<31, 3<<29);
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@ -1048,7 +1083,7 @@ dumptiming(char *name, Trans *t)
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int tu, m, n;
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if(t->dm[0].a != 0 && t->dm[0].v != 0){
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tu = (t->dm[0].v >> 25)+1;
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tu = 1+((t->dm[0].v >> 25) & 0x3f);
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printitem(name, "dm1 tu");
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Bprint(&stdout, " %d\n", tu);
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@ -1128,6 +1163,54 @@ dumppipe(Igfx *igfx, int x)
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dumpreg(name, "pos", p->cur->pos);
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}
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static void
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dumpdpll(Igfx *igfx, int x)
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{
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int cref, m1, m2, n, p1, p2;
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uvlong freq;
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char name[32];
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Dpll *dpll;
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u32int m;
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dpll = &igfx->dpll[x];
|
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snprint(name, sizeof(name), "%s dpll %c", igfx->ctlr->name, 'a'+x);
|
||||
|
||||
dumpreg(name, "ctrl", dpll->ctrl);
|
||||
dumpreg(name, "fp0", dpll->fp0);
|
||||
dumpreg(name, "fp1", dpll->fp1);
|
||||
|
||||
p2 = ((dpll->ctrl.v >> 13) & 3) == 3 ? 14 : 10;
|
||||
if(((dpll->ctrl.v >> 24) & 3) == 1)
|
||||
p2 >>= 1;
|
||||
m = (dpll->ctrl.v >> 16) & 0xFF;
|
||||
for(p1 = 1; p1 <= 8; p1++)
|
||||
if(m & (1<<(p1-1)))
|
||||
break;
|
||||
printitem(name, "ctrl p1");
|
||||
Bprint(&stdout, " %d\n", p1);
|
||||
printitem(name, "ctrl p2");
|
||||
Bprint(&stdout, " %d\n", p2);
|
||||
|
||||
n = (dpll->fp0.v >> 16) & 0x3f;
|
||||
m1 = (dpll->fp0.v >> 8) & 0x3f;
|
||||
m2 = (dpll->fp0.v >> 0) & 0x3f;
|
||||
|
||||
cref = getcref(igfx, x);
|
||||
freq = ((uvlong)cref * (5*(m1+2) + (m2+2)) / (n+2)) / (p1 * p2);
|
||||
|
||||
printitem(name, "fp0 m1");
|
||||
Bprint(&stdout, " %d\n", m1);
|
||||
printitem(name, "fp0 m2");
|
||||
Bprint(&stdout, " %d\n", m2);
|
||||
printitem(name, "fp0 n");
|
||||
Bprint(&stdout, " %d\n", n);
|
||||
|
||||
printitem(name, "cref");
|
||||
Bprint(&stdout, " %d\n", cref);
|
||||
printitem(name, "fp0 freq");
|
||||
Bprint(&stdout, " %lld\n", freq);
|
||||
}
|
||||
|
||||
static void
|
||||
dump(Vga* vga, Ctlr* ctlr)
|
||||
{
|
||||
|
|
@ -1141,12 +1224,8 @@ dump(Vga* vga, Ctlr* ctlr)
|
|||
for(x=0; x<igfx->npipe; x++)
|
||||
dumppipe(igfx, x);
|
||||
|
||||
for(x=0; x<nelem(igfx->dpll); x++){
|
||||
snprint(name, sizeof(name), "%s dpll %c", ctlr->name, 'a'+x);
|
||||
dumpreg(name, "ctrl", igfx->dpll[x].ctrl);
|
||||
dumpreg(name, "fp0", igfx->dpll[x].fp0);
|
||||
dumpreg(name, "fp1", igfx->dpll[x].fp1);
|
||||
}
|
||||
for(x=0; x<nelem(igfx->dpll); x++)
|
||||
dumpdpll(igfx, x);
|
||||
|
||||
dumpreg(ctlr->name, "dpllsel", igfx->dpllsel);
|
||||
|
||||
|
|
@ -1181,8 +1260,14 @@ dump(Vga* vga, Ctlr* ctlr)
|
|||
|
||||
dumpreg(ctlr->name, "vgacntrl", igfx->vgacntrl);
|
||||
|
||||
if(igfx->lvdsedid != nil)
|
||||
if(igfx->adpaedid != nil){
|
||||
Bprint(&stdout, "edid adpa\n");
|
||||
printedid(igfx->adpaedid);
|
||||
}
|
||||
if(igfx->lvdsedid != nil){
|
||||
Bprint(&stdout, "edid lvds\n");
|
||||
printedid(igfx->lvdsedid);
|
||||
}
|
||||
}
|
||||
|
||||
enum {
|
||||
|
|
@ -1195,7 +1280,7 @@ enum {
|
|||
};
|
||||
|
||||
static int
|
||||
gmbusread(Igfx *igfx, int portsel, int addr, uchar *data, int len)
|
||||
gmbusread(Igfx *igfx, int port, int addr, uchar *data, int len)
|
||||
{
|
||||
u32int x, y;
|
||||
int n, t;
|
||||
|
|
@ -1203,7 +1288,7 @@ gmbusread(Igfx *igfx, int portsel, int addr, uchar *data, int len)
|
|||
if(igfx->gmbus[GMBUSCP].a == 0)
|
||||
return -1;
|
||||
|
||||
wr(igfx, igfx->gmbus[GMBUSCP].a, portsel);
|
||||
wr(igfx, igfx->gmbus[GMBUSCP].a, port);
|
||||
wr(igfx, igfx->gmbus[GMBUSIX].a, 0);
|
||||
|
||||
/* bus cycle without index and stop, byte count, slave address, read */
|
||||
|
|
@ -1238,21 +1323,41 @@ gmbusread(Igfx *igfx, int portsel, int addr, uchar *data, int len)
|
|||
data[n++] = y & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
static void
|
||||
snarfedid(Igfx *igfx)
|
||||
static Edid*
|
||||
snarfedid(Igfx *igfx, int port, int addr)
|
||||
{
|
||||
uchar buf[128];
|
||||
uchar buf[256], tmp[256];
|
||||
Edid *e;
|
||||
int i;
|
||||
|
||||
if(gmbusread(igfx, 3, 0x50, buf, sizeof(buf)) != sizeof(buf))
|
||||
return;
|
||||
igfx->lvdsedid = malloc(sizeof(Edid));
|
||||
if(parseedid128(igfx->lvdsedid, buf) != 0){
|
||||
free(igfx->lvdsedid);
|
||||
igfx->lvdsedid = nil;
|
||||
/* read twice */
|
||||
if(gmbusread(igfx, port, addr, buf, 128) != 128)
|
||||
return nil;
|
||||
if(gmbusread(igfx, port, addr, buf + 128, 128) != 128)
|
||||
return nil;
|
||||
|
||||
/* shift if neccesary so edid block is at the start */
|
||||
for(i=0; i<256-8; i++){
|
||||
if(buf[i+0] == 0x00 && buf[i+1] == 0xFF && buf[i+2] == 0xFF && buf[i+3] == 0xFF
|
||||
&& buf[i+4] == 0xFF && buf[i+5] == 0xFF && buf[i+6] == 0xFF && buf[i+7] == 0x00){
|
||||
memmove(tmp, buf, i);
|
||||
memmove(buf, buf + i, 256 - i);
|
||||
memmove(buf + (256 - i), tmp, i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
e = malloc(sizeof(Edid));
|
||||
if(parseedid128(e, buf) != 0){
|
||||
free(e);
|
||||
return nil;
|
||||
}
|
||||
|
||||
return e;
|
||||
}
|
||||
|
||||
Ctlr igfx = {
|
||||
|
|
|
|||
Loading…
Reference in a new issue