etherrt2860: add rt3090 support and make style more consistent
This commit is contained in:
ppatience0
parent
776056dcd0
commit
9a5763624f
1 changed files with 657 additions and 109 deletions
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@ -783,6 +783,33 @@ enum {
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Rf3053 = 13 /* dual-band 3T3R */,
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};
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enum {
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Rt3070RfBlock = (1 << 0),
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Rt3070Rx0Pd = (1 << 2),
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Rt3070Tx0Pd = (1 << 3),
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Rt3070Rx1Pd = (1 << 4),
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Rt3070Tx1Pd = (1 << 5),
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Rt3070Rx2Pd = (1 << 6),
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Rt3070Tx2Pd = (1 << 7),
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Rt3070Tune = (1 << 0),
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Rt3070TxLo2 = (1 << 3),
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Rt3070TxLo1 = (1 << 3),
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Rt3070RxLo1 = (1 << 3),
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Rt3070RxLo2 = (1 << 3),
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Rt3070RxCtb = (1 << 7),
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Rt3070BbLoopback = (1 << 0),
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Rt3593Vco = (1 << 0),
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Rt3593Rescal = (1 << 7),
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Rt3593Vcocal = (1 << 7),
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Rt3593VcoIc = (1 << 6),
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Rt3593LdoPllVcMask = 0x0e,
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Rt3593LdoRfVcMask = 0xe0,
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Rt3593CpIcMask = 0xe0,
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Rt3593CpIcShift = 5,
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Rt3593RxCtb = (1 << 5)
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};
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static const char* rfnames[] = {
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[Rf2820] "RT2820",
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[Rf2850] "RT2850",
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@ -976,7 +1003,6 @@ enum {
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ConnPciE = 1 << 1,
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};
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static const struct rt2860_rate {
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u8int rate;
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u8int mcs;
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@ -1122,6 +1148,91 @@ static const struct rfprog {
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{ 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 },
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};
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struct {
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u8int n;
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u8int r;
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u8int k;
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} rt3090_freqs[] = {
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{ 0xf1, 2, 2 },
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{ 0xf1, 2, 7 },
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{ 0xf2, 2, 2 },
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{ 0xf2, 2, 7 },
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{ 0xf3, 2, 2 },
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{ 0xf3, 2, 7 },
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{ 0xf4, 2, 2 },
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{ 0xf4, 2, 7 },
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{ 0xf5, 2, 2 },
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{ 0xf5, 2, 7 },
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{ 0xf6, 2, 2 },
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{ 0xf6, 2, 7 },
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{ 0xf7, 2, 2 },
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{ 0xf8, 2, 4 },
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{ 0x56, 0, 4 },
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{ 0x56, 0, 6 },
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{ 0x56, 0, 8 },
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{ 0x57, 0, 0 },
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{ 0x57, 0, 2 },
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{ 0x57, 0, 4 },
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{ 0x57, 0, 8 },
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{ 0x57, 0, 10 },
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{ 0x58, 0, 0 },
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{ 0x58, 0, 4 },
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{ 0x58, 0, 6 },
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{ 0x58, 0, 8 },
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{ 0x5b, 0, 8 },
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{ 0x5b, 0, 10 },
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{ 0x5c, 0, 0 },
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{ 0x5c, 0, 4 },
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{ 0x5c, 0, 6 },
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{ 0x5c, 0, 8 },
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{ 0x5d, 0, 0 },
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{ 0x5d, 0, 2 },
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{ 0x5d, 0, 4 },
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{ 0x5d, 0, 8 },
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{ 0x5d, 0, 10 },
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{ 0x5e, 0, 0 },
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{ 0x5e, 0, 4 },
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{ 0x5e, 0, 6 },
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{ 0x5e, 0, 8 },
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{ 0x5f, 0, 0 },
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{ 0x5f, 0, 9 },
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{ 0x5f, 0, 11 },
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{ 0x60, 0, 1 },
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{ 0x60, 0, 5 },
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{ 0x60, 0, 7 },
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{ 0x60, 0, 9 },
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{ 0x61, 0, 1 },
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{ 0x61, 0, 3 },
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{ 0x61, 0, 5 },
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{ 0x61, 0, 7 },
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{ 0x61, 0, 9 }
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};
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static const struct {
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u8int reg;
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u8int val;
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} rt3090_def_rf[] = {
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{ 4, 0x40 },
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{ 5, 0x03 },
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{ 6, 0x02 },
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{ 7, 0x70 },
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{ 9, 0x0f },
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{ 10, 0x41 },
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{ 11, 0x21 },
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{ 12, 0x7b },
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{ 14, 0x90 },
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{ 15, 0x58 },
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{ 16, 0xb3 },
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{ 17, 0x92 },
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{ 18, 0x2c },
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{ 19, 0x02 },
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{ 20, 0xba },
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{ 21, 0xdb },
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{ 24, 0x16 },
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{ 25, 0x01 },
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{ 29, 0x1f }
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};
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/* vendors */
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enum {
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Ralink = 0x1814,
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@ -1131,6 +1242,7 @@ enum {
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enum {
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RalinkRT2890 = 0x0681,
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RalinkRT2790 = 0x0781,
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RalinkRT3090 = 0x3090,
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AwtRT2890 = 0x1059,
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};
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@ -1139,6 +1251,7 @@ enum {
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static int rbplant(Ctlr*, int);
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static void setchan(Ctlr*, uint);
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static void rt3090setchan(Ctlr*, uint);
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static void selchangroup(Ctlr*, int);
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static void setleds(Ctlr*, u16int);
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@ -1242,6 +1355,9 @@ rxon(Ether *edev, Wnode *bss)
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edev->ctlrno, ctlr->bssid, ctlr->aid, ctlr->channel, ctlr->wcid);
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/* Set channel */
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if(ctlr->mac_ver >= 0x3071)
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rt3090setchan(ctlr, ctlr->channel);
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else
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setchan(ctlr, ctlr->channel);
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selchangroup(ctlr, 0);
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microdelay(1000);
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@ -1600,7 +1716,7 @@ txrxon(Ctlr *ctlr)
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/*
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* Write to one of the 4 programmable 24-bit RF registers.
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*/
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static char*
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static void
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rfwrite(Ctlr *ctlr, u8int reg, u32int val)
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{
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u32int tmp;
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@ -1611,14 +1727,66 @@ rfwrite(Ctlr *ctlr, u8int reg, u32int val)
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break;
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microdelay(1);
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}
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if(ntries == 100)
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return "could not write to RF";
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if(ntries == 100){
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print("could not write to RF\n");
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return;
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}
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/* RF registers are 24-bit on the RT2860 */
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tmp = RfRegCtrl | 24 << RfRegWidthShift |
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(val & 0x3fffff) << 2 | (reg & 3);
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csr32w(ctlr, RfCsrCfg0, tmp);
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return nil;
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}
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u8int
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rt3090rfread(Ctlr *ctlr, u8int reg)
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{
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u32int tmp;
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int ntries;
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for(ntries = 0; ntries < 100; ntries++){
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if(!(csr32r(ctlr, Rt3070RfCsrCfg) & Rt3070RfKick))
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break;
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microdelay(1);
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}
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if(ntries == 100){
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print("could not read RF register\n");
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return 0xff;
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}
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tmp = Rt3070RfKick | reg << 8;
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csr32w(ctlr, Rt3070RfCsrCfg, tmp);
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for(ntries = 0; ntries < 100; ntries++){
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tmp = csr32r(ctlr, Rt3070RfCsrCfg);
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if(!(tmp & Rt3070RfKick))
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break;
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microdelay(1);
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}
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if(ntries == 100){
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print("could not read RF register\n");
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return 0xff;
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}
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return tmp & 0xff;
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}
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static void
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rt3090rfwrite(Ctlr *ctlr, u8int reg, u8int val)
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{
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u32int tmp;
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int ntries;
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for(ntries = 0; ntries < 10; ntries++){
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if(!(csr32r(ctlr, Rt3070RfCsrCfg) & Rt3070RfKick))
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break;
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microdelay(10);
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}
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if(ntries == 10){
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print("could not write to RF\n");
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return;
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}
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tmp = Rt3070RfWrite | Rt3070RfKick | reg << 8 | val;
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csr32w(ctlr, Rt3070RfCsrCfg, tmp);
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}
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static void
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@ -1761,6 +1929,356 @@ setchan(Ctlr *ctlr, uint chan)
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rfwrite(ctlr, Rf4, r4);
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}
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static void
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rt3090setchan(Ctlr *ctlr, uint chan)
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{
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s8int txpow1, txpow2;
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u8int rf;
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int i;
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assert(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */
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/* find the settings for this channel (we know it exists) */
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for(i = 0; rt2860_rf2850[i].chan != chan; i++);
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/* use Tx power values from EEPROM */
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txpow1 = ctlr->txpow1[i];
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txpow2 = ctlr->txpow2[i];
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rt3090rfwrite(ctlr, 2, rt3090_freqs[i].n);
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rf = rt3090rfread(ctlr, 3);
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rf = (rf & ~0x0f) | rt3090_freqs[i].k;
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rt3090rfwrite(ctlr, 3, rf);
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rf = rt3090rfread(ctlr, 6);
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rf = (rf & ~0x03) | rt3090_freqs[i].r;
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rt3090rfwrite(ctlr, 6, rf);
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/* set Tx0 power */
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rf = rt3090rfread(ctlr, 12);
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rf = (rf & ~0x1f) | txpow1;
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rt3090rfwrite(ctlr, 12, rf);
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/* set Tx1 power */
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rf = rt3090rfread(ctlr, 13);
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rf = (rf & ~0x1f) | txpow2;
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rt3090rfwrite(ctlr, 13, rf);
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rf = rt3090rfread(ctlr, 1);
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rf &= ~0xfc;
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if(ctlr->ntxchains == 1)
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rf |= Rt3070Tx1Pd | Rt3070Tx2Pd;
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else if(ctlr->ntxchains == 2)
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rf |= Rt3070Tx2Pd;
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if(ctlr->nrxchains == 1)
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rf |= Rt3070Rx1Pd | Rt3070Rx2Pd;
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else if(ctlr->nrxchains == 2)
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rf |= Rt3070Rx2Pd;
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rt3090rfwrite(ctlr, 1, rf);
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/* set RF offset */
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rf = rt3090rfread(ctlr, 23);
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rf = (rf & ~0x7f) | ctlr->freq;
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rt3090rfwrite(ctlr, 23, rf);
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/* program RF filter */
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rf = rt3090rfread(ctlr, 24); /* Tx */
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rf = (rf & ~0x3f) | ctlr->rf24_20mhz;
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rt3090rfwrite(ctlr, 24, rf);
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rf = rt3090rfread(ctlr, 31); /* Rx */
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rf = (rf & ~0x3f) | ctlr->rf24_20mhz;
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rt3090rfwrite(ctlr, 31, rf);
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/* enable RF tuning */
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rf = rt3090rfread(ctlr, 7);
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rt3090rfwrite(ctlr, 7, rf | Rt3070Tune);
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}
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static int
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rt3090filtercalib(Ctlr *ctlr, u8int init, u8int target, u8int *val)
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{
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u8int rf22, rf24;
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u8int bbp55_pb, bbp55_sb, delta;
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int ntries;
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/* program filter */
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rf24 = rt3090rfread(ctlr, 24);
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rf24 = (rf24 & 0xc0) | init; /* initial filter value */
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rt3090rfwrite(ctlr, 24, rf24);
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/* enable baseband loopback mode */
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rf22 = rt3090rfread(ctlr, 22);
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rt3090rfwrite(ctlr, 22, rf22 | Rt3070BbLoopback);
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/* set power and frequency of passband test tone */
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bbpwrite(ctlr, 24, 0x00);
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for(ntries = 0, bbp55_pb = 0; ntries < 100; ntries++){
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/* transmit test tone */
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bbpwrite(ctlr, 25, 0x90);
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microdelay(1000);
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/* read received power */
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bbp55_pb = bbpread(ctlr, 55);
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if(bbp55_pb != 0)
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break;
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}
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if(ntries == 100)
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return -1;
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/* set power and frequency of stopband test tone */
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bbpwrite(ctlr, 24, 0x06);
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for(ntries = 0; ntries < 100; ntries++){
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/* transmit test tone */
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bbpwrite(ctlr, 25, 0x90);
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microdelay(1000);
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/* read received power */
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bbp55_sb = bbpread(ctlr, 55);
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delta = bbp55_pb - bbp55_sb;
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if(delta > target)
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break;
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/* reprogram filter */
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rf24++;
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rt3090rfwrite(ctlr, 24, rf24);
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}
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if(ntries < 100){
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if(rf24 != init)
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rf24--; /* backtrack */
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*val = rf24;
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rt3090rfwrite(ctlr, 24, rf24);
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}
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/* restore initial state */
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bbpwrite(ctlr, 24, 0x00);
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/* disable baseband loopback mode */
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rf22 = rt3090rfread(ctlr, 22);
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rt3090rfwrite(ctlr, 22, rf22 & ~Rt3070BbLoopback);
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return 0;
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}
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static void
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rt3090setrxantenna(Ctlr *ctlr, int aux)
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{
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u32int tmp;
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if(aux){
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tmp = csr32r(ctlr, PciEectrl);
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csr32w(ctlr, PciEectrl, tmp & ~EectrlC);
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tmp = csr32r(ctlr, GpioCtrl);
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csr32w(ctlr, GpioCtrl, (tmp & ~0x0808) | 0x08);
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}else{
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tmp = csr32r(ctlr, PciEectrl);
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csr32w(ctlr, PciEectrl, tmp | EectrlC);
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tmp = csr32r(ctlr, GpioCtrl);
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csr32w(ctlr, GpioCtrl, tmp & ~0x0808);
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}
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}
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static int
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rt3090rfinit(Ctlr *ctlr)
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{
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u32int tmp;
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u8int rf, bbp;
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int i;
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rf = rt3090rfread(ctlr, 30);
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/* toggle RF R30 bit 7 */
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rt3090rfwrite(ctlr, 30, rf | 0x80);
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microdelay(1000);
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rt3090rfwrite(ctlr, 30, rf & ~0x80);
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tmp = csr32r(ctlr, Rt3070LdoCfg0);
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tmp &= ~0x1f000000;
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if(ctlr->patch_dac && ctlr->mac_rev < 0x0211)
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tmp |= 0x0d000000; /* 1.35V */
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else
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tmp |= 0x01000000; /* 1.2V */
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csr32w(ctlr, Rt3070LdoCfg0, tmp);
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/* patch LNA_PE_G1 */
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tmp = csr32r(ctlr, Rt3070GpioSwitch);
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csr32w(ctlr, Rt3070GpioSwitch, tmp & ~0x20);
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/* initialize RF registers to default value */
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for(i = 0; i < nelem(rt3090_def_rf); i++){
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rt3090rfwrite(ctlr, rt3090_def_rf[i].reg,
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rt3090_def_rf[i].val);
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}
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/* select 20MHz bandwidth */
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rt3090rfwrite(ctlr, 31, 0x14);
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rf = rt3090rfread(ctlr, 6);
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rt3090rfwrite(ctlr, 6, rf | 0x40);
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if(ctlr->mac_ver != 0x3593){
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/* calibrate filter for 20MHz bandwidth */
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ctlr->rf24_20mhz = 0x1f; /* default value */
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rt3090filtercalib(ctlr, 0x07, 0x16, &ctlr->rf24_20mhz);
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/* select 40MHz bandwidth */
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bbp = bbpread(ctlr, 4);
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bbpwrite(ctlr, 4, (bbp & ~0x08) | 0x10);
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rf = rt3090rfread(ctlr, 31);
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rt3090rfwrite(ctlr, 31, rf | 0x20);
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/* calibrate filter for 40MHz bandwidth */
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ctlr->rf24_40mhz = 0x2f; /* default value */
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rt3090filtercalib(ctlr, 0x27, 0x19, &ctlr->rf24_40mhz);
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/* go back to 20MHz bandwidth */
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bbp = bbpread(ctlr, 4);
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bbpwrite(ctlr, 4, bbp & ~0x18);
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}
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if(ctlr->mac_rev < 0x0211)
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rt3090rfwrite(ctlr, 27, 0x03);
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tmp = csr32r(ctlr, Rt3070Opt14);
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csr32w(ctlr, Rt3070Opt14, tmp | 1);
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|
||||
if(ctlr->rf_rev == Rf3020)
|
||||
rt3090setrxantenna(ctlr, 0);
|
||||
|
||||
bbp = bbpread(ctlr, 138);
|
||||
if(ctlr->mac_ver == 0x3593){
|
||||
if(ctlr->ntxchains == 1)
|
||||
bbp |= 0x60; /* turn off DAC1 and DAC2 */
|
||||
else if(ctlr->ntxchains == 2)
|
||||
bbp |= 0x40; /* turn off DAC2 */
|
||||
if(ctlr->nrxchains == 1)
|
||||
bbp &= ~0x06; /* turn off ADC1 and ADC2 */
|
||||
else if(ctlr->nrxchains == 2)
|
||||
bbp &= ~0x04; /* turn off ADC2 */
|
||||
}else{
|
||||
if(ctlr->ntxchains == 1)
|
||||
bbp |= 0x20; /* turn off DAC1 */
|
||||
if(ctlr->nrxchains == 1)
|
||||
bbp &= ~0x02; /* turn off ADC1 */
|
||||
}
|
||||
bbpwrite(ctlr, 138, bbp);
|
||||
|
||||
rf = rt3090rfread(ctlr, 1);
|
||||
rf &= ~(Rt3070Rx0Pd | Rt3070Tx0Pd);
|
||||
rf |= Rt3070RfBlock | Rt3070Rx1Pd | Rt3070Tx1Pd;
|
||||
rt3090rfwrite(ctlr, 1, rf);
|
||||
|
||||
rf = rt3090rfread(ctlr, 15);
|
||||
rt3090rfwrite(ctlr, 15, rf & ~Rt3070TxLo2);
|
||||
|
||||
rf = rt3090rfread(ctlr, 17);
|
||||
rf &= ~Rt3070TxLo1;
|
||||
if(ctlr->mac_rev >= 0x0211 && !ctlr->ext_2ghz_lna)
|
||||
rf |= 0x20; /* fix for long range Rx issue */
|
||||
if(ctlr->txmixgain_2ghz >= 2)
|
||||
rf = (rf & ~0x7) | ctlr->txmixgain_2ghz;
|
||||
rt3090rfwrite(ctlr, 17, rf);
|
||||
|
||||
rf = rt3090rfread(ctlr, 20);
|
||||
rt3090rfwrite(ctlr, 20, rf & ~Rt3070RxLo1);
|
||||
|
||||
rf = rt3090rfread(ctlr, 21);
|
||||
rt3090rfwrite(ctlr, 21, rf & ~Rt3070RxLo2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
rt3090rfwakeup(Ctlr *ctlr)
|
||||
{
|
||||
u32int tmp;
|
||||
u8int rf;
|
||||
|
||||
if(ctlr->mac_ver == 0x3593){
|
||||
/* enable VCO */
|
||||
rf = rt3090rfread(ctlr, 1);
|
||||
rt3090rfwrite(ctlr, 1, rf | Rt3593Vco);
|
||||
|
||||
/* initiate VCO calibration */
|
||||
rf = rt3090rfread(ctlr, 3);
|
||||
rt3090rfwrite(ctlr, 3, rf | Rt3593Vcocal);
|
||||
|
||||
/* enable VCO bias current control */
|
||||
rf = rt3090rfread(ctlr, 6);
|
||||
rt3090rfwrite(ctlr, 6, rf | Rt3593VcoIc);
|
||||
|
||||
/* initiate res calibration */
|
||||
rf = rt3090rfread(ctlr, 2);
|
||||
rt3090rfwrite(ctlr, 2, rf | Rt3593Rescal);
|
||||
|
||||
/* set reference current control to 0.33 mA */
|
||||
rf = rt3090rfread(ctlr, 22);
|
||||
rf &= ~Rt3593CpIcMask;
|
||||
rf |= 1 << Rt3593CpIcShift;
|
||||
rt3090rfwrite(ctlr, 22, rf);
|
||||
|
||||
/* enable RX CTB */
|
||||
rf = rt3090rfread(ctlr, 46);
|
||||
rt3090rfwrite(ctlr, 46, rf | Rt3593RxCtb);
|
||||
|
||||
rf = rt3090rfread(ctlr, 20);
|
||||
rf &= ~(Rt3593LdoRfVcMask | Rt3593LdoPllVcMask);
|
||||
rt3090rfwrite(ctlr, 20, rf);
|
||||
}else{
|
||||
/* enable RF block */
|
||||
rf = rt3090rfread(ctlr, 1);
|
||||
rt3090rfwrite(ctlr, 1, rf | Rt3070RfBlock);
|
||||
|
||||
/* enable VCO bias current control */
|
||||
rf = rt3090rfread(ctlr, 7);
|
||||
rt3090rfwrite(ctlr, 7, rf | 0x30);
|
||||
|
||||
rf = rt3090rfread(ctlr, 9);
|
||||
rt3090rfwrite(ctlr, 9, rf | 0x0e);
|
||||
|
||||
/* enable RX CTB */
|
||||
rf = rt3090rfread(ctlr, 21);
|
||||
rt3090rfwrite(ctlr, 21, rf | Rt3070RxCtb);
|
||||
|
||||
/* fix Tx to Rx IQ glitch by raising RF voltage */
|
||||
rf = rt3090rfread(ctlr, 27);
|
||||
rf &= ~0x77;
|
||||
if(ctlr->mac_rev < 0x0211)
|
||||
rf |= 0x03;
|
||||
rt3090rfwrite(ctlr, 27, rf);
|
||||
}
|
||||
if(ctlr->patch_dac && ctlr->mac_rev < 0x0211){
|
||||
tmp = csr32r(ctlr, Rt3070LdoCfg0);
|
||||
tmp = (tmp & ~0x1f000000) | 0x0d000000;
|
||||
csr32w(ctlr, Rt3070LdoCfg0, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rt3090rfsetup(Ctlr *ctlr)
|
||||
{
|
||||
u8int bbp;
|
||||
int i;
|
||||
|
||||
if(ctlr->mac_rev >= 0x0211){
|
||||
/* enable DC filter */
|
||||
bbpwrite(ctlr, 103, 0xc0);
|
||||
|
||||
/* improve power consumption */
|
||||
bbp = bbpread(ctlr, 31);
|
||||
bbpwrite(ctlr, 31, bbp & ~0x03);
|
||||
}
|
||||
|
||||
csr32w(ctlr, TxSwCfg1, 0);
|
||||
if(ctlr->mac_rev < 0x0211){
|
||||
csr32w(ctlr, TxSwCfg2,
|
||||
ctlr->patch_dac ? 0x2c : 0x0f);
|
||||
}else
|
||||
csr32w(ctlr, TxSwCfg2, 0);
|
||||
|
||||
/* initialize RF registers from ROM */
|
||||
for(i = 0; i < 10; i++){
|
||||
if(ctlr->rf[i].reg == 0 || ctlr->rf[i].reg == 0xff)
|
||||
continue;
|
||||
rt3090rfwrite(ctlr, ctlr->rf[i].reg, ctlr->rf[i].val);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
updateprot(Ctlr *ctlr)
|
||||
{
|
||||
|
|
@ -1945,29 +2463,24 @@ rt2860start(Ether *edev)
|
|||
}
|
||||
|
||||
/* select Main antenna for 1T1R devices */
|
||||
/* notyet
|
||||
if(ctlr->rf_rev == Rf2020 ||
|
||||
ctlr->rf_rev == Rf3020 ||
|
||||
ctlr->rf_rev == Rf3320)
|
||||
rt3090_set_rx_antenna(ctlr, 0);
|
||||
*/
|
||||
rt3090setrxantenna(ctlr, 0);
|
||||
|
||||
/* send LEDs operating mode to microcontroller */
|
||||
mcucmd(ctlr, McuCmdLed1, ctlr->led[0], 0);
|
||||
mcucmd(ctlr, McuCmdLed2, ctlr->led[1], 0);
|
||||
mcucmd(ctlr, McuCmdLed3, ctlr->led[2], 0);
|
||||
|
||||
/* XXX: 30xx
|
||||
if(ctlr->mac_ver >= 0x3071)
|
||||
rt3090_rf_init(ctlr);
|
||||
*/
|
||||
rt3090rfinit(ctlr);
|
||||
|
||||
mcucmd(ctlr, McuCmdSleep, 0x02ff, 1);
|
||||
mcucmd(ctlr, McuCmdWakeup, 0, 1);
|
||||
/* XXX: 30xx
|
||||
|
||||
if(ctlr->mac_ver >= 0x3071)
|
||||
rt3090_rf_wakeup(ctlr);
|
||||
*/
|
||||
rt3090rfwakeup(ctlr);
|
||||
|
||||
/* disable non-existing Rx chains */
|
||||
bbp3 = bbpread(ctlr, 3);
|
||||
|
|
@ -1987,11 +2500,14 @@ rt2860start(Ether *edev)
|
|||
else if(ctlr->mac_ver == 0x3593 && ctlr->ntxchains == 3)
|
||||
bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
|
||||
bbpwrite(ctlr, 1, bbp1);
|
||||
/* XXX: 30xx
|
||||
|
||||
if(ctlr->mac_ver >= 0x3071)
|
||||
rt3090_rf_setup(ctlr);
|
||||
*/
|
||||
rt3090rfsetup(ctlr);
|
||||
|
||||
/* select default channel */
|
||||
if(ctlr->mac_ver >= 0x3071)
|
||||
rt3090setchan(ctlr, 3);
|
||||
else
|
||||
setchan(ctlr, 3);
|
||||
|
||||
/* reset RF from MCU */
|
||||
|
|
@ -2450,11 +2966,41 @@ eeread2(Ctlr *ctlr, u16int addr)
|
|||
|
||||
/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
|
||||
static u16int
|
||||
efuseread2(Ctlr *, u16int)
|
||||
efuseread2(Ctlr *ctlr, u16int addr)
|
||||
{
|
||||
/* XXX: 30xx */
|
||||
print("efuse rom not implemented\n");
|
||||
return 0;
|
||||
u32int tmp;
|
||||
u16int reg;
|
||||
int ntries;
|
||||
|
||||
addr *= 2;
|
||||
/*-
|
||||
* Read one 16-byte block into registers EFUSE_DATA[0-3]:
|
||||
* DATA0: F E D C
|
||||
* DATA1: B A 9 8
|
||||
* DATA2: 7 6 5 4
|
||||
* DATA3: 3 2 1 0
|
||||
*/
|
||||
tmp = csr32r(ctlr, Rt3070EfuseCtrl);
|
||||
tmp &= ~(Rt3070EfsromModeMask | Rt3070EfsromAinMask);
|
||||
tmp |= (addr & ~0xf) << Rt3070EfsromAinShift | Rt3070EfsromKick;
|
||||
csr32w(ctlr, Rt3070EfuseCtrl, tmp);
|
||||
for(ntries = 0; ntries < 500; ntries++){
|
||||
tmp = csr32r(ctlr, Rt3070EfuseCtrl);
|
||||
if(!(tmp & Rt3070EfsromKick))
|
||||
break;
|
||||
microdelay(2);
|
||||
}
|
||||
if(ntries == 500)
|
||||
return 0xffff;
|
||||
|
||||
if((tmp & Rt3070EfuseAoutMask) == Rt3070EfuseAoutMask)
|
||||
return 0xffff; /* address not found */
|
||||
|
||||
/* determine to which 32-bit register our 16-bit word belongs */
|
||||
reg = Rt3070EfuseData3 - (addr & 0xc);
|
||||
tmp = csr32r(ctlr, reg);
|
||||
|
||||
return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
|
||||
}
|
||||
|
||||
static char*
|
||||
|
|
@ -2903,6 +3449,7 @@ rt2860init(Ether *edev)
|
|||
break;
|
||||
case RalinkRT2890:
|
||||
case RalinkRT2790:
|
||||
case RalinkRT3090:
|
||||
case AwtRT2890:
|
||||
ctlr->flags = AdvancedPs;
|
||||
break;
|
||||
|
|
@ -2942,7 +3489,8 @@ rt2860pci(void)
|
|||
switch(pdev->did){
|
||||
default:
|
||||
continue;
|
||||
case 0x0781: /* RT2790 */
|
||||
case RalinkRT2790:
|
||||
case RalinkRT3090:
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue