diff --git a/sys/src/9/imx8/fns.h b/sys/src/9/imx8/fns.h
index 17ff2ec49..d0f276a53 100644
--- a/sys/src/9/imx8/fns.h
+++ b/sys/src/9/imx8/fns.h
@@ -150,3 +150,6 @@ extern void powerup(char *dom);
 
 /* lcd */
 extern void lcdinit(void);
+
+/* iomuc */
+extern void iomuxpad(char *pads, char *sel, char *cfg);
diff --git a/sys/src/9/imx8/iomux.c b/sys/src/9/imx8/iomux.c
new file mode 100644
index 000000000..73184e74e
--- /dev/null
+++ b/sys/src/9/imx8/iomux.c
@@ -0,0 +1,1125 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+
+static u32int *iomuxc = (u32int*)(VIRTIO + 0x330000);
+
+enum {
+	IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ = 0x014/4,
+		SION = 1<<4,
+		MUX_MODE = 7,
+
+	IOMUXC_SW_PAD_CTL_PAD_TEST_MODE	= 0x254/4,
+		
+	IOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0x4BC/4,
+};
+
+enum {
+	/* pads without muxes */
+	PAD_TEST_MODE = 0,
+
+	PAD_BOOT_MODE0, PAD_BOOT_MODE1,
+
+	PAD_JTAG_MOD, PAD_JTAG_TRST_B, PAD_JTAG_TDI, PAD_JTAG_TMS,
+	PAD_JTAG_TCK, PAD_JTAG_TDO,
+
+	PAD_RTC,
+
+	PAD_PMIC_STBY_REQ, PAD_PMIC_ON_REQ,
+	PAD_ONOFF, PAD_POR_B, PAD_RTC_RESET_B,
+
+	/* pads with muxes */
+	PAD_GPIO1_IO00, PAD_GPIO1_IO01, PAD_GPIO1_IO02, PAD_GPIO1_IO03,
+	PAD_GPIO1_IO04, PAD_GPIO1_IO05, PAD_GPIO1_IO06, PAD_GPIO1_IO07,
+	PAD_GPIO1_IO08, PAD_GPIO1_IO09, PAD_GPIO1_IO10, PAD_GPIO1_IO11,
+	PAD_GPIO1_IO12, PAD_GPIO1_IO13, PAD_GPIO1_IO14, PAD_GPIO1_IO15,
+
+	PAD_ENET_MDC, PAD_ENET_MDIO,
+	PAD_ENET_TD3, PAD_ENET_TD2, PAD_ENET_TD1, PAD_ENET_TD0,
+	PAD_ENET_TX_CTL, PAD_ENET_TXC, PAD_ENET_RX_CTL, PAD_ENET_RXC,
+	PAD_ENET_RD0, PAD_ENET_RD1, PAD_ENET_RD2, PAD_ENET_RD3,
+
+	PAD_SD1_CLK, PAD_SD1_CMD, PAD_SD1_DATA0, PAD_SD1_DATA1,
+	PAD_SD1_DATA2, PAD_SD1_DATA3, PAD_SD1_DATA4, PAD_SD1_DATA5,
+	PAD_SD1_DATA6, PAD_SD1_DATA7, PAD_SD1_RESET_B, PAD_SD1_STROBE,
+
+	PAD_SD2_CD_B, PAD_SD2_CLK, PAD_SD2_CMD, PAD_SD2_DATA0,
+	PAD_SD2_DATA1, PAD_SD2_DATA2, PAD_SD2_DATA3, 
+	PAD_SD2_RESET_B, PAD_SD2_WP,
+
+	PAD_NAND_ALE, PAD_NAND_CE0_B, PAD_NAND_CE1_B, PAD_NAND_CE2_B,
+	PAD_NAND_CE3_B, PAD_NAND_CLE, PAD_NAND_DATA0, PAD_NAND_DATA1,
+	PAD_NAND_DATA2, PAD_NAND_DATA3, PAD_NAND_DATA4,
+	PAD_NAND_DATA5, PAD_NAND_DATA6, PAD_NAND_DATA7, PAD_NAND_DQS,
+	PAD_NAND_RE_B, PAD_NAND_READY_B, PAD_NAND_WE_B, PAD_NAND_WP_B,
+
+	PAD_SAI5_RXFS, PAD_SAI5_RXC, PAD_SAI5_RXD0, PAD_SAI5_RXD1,
+	PAD_SAI5_RXD2, PAD_SAI5_RXD3, PAD_SAI5_MCLK,
+
+	PAD_SAI1_RXFS, PAD_SAI1_RXC, PAD_SAI1_RXD0, PAD_SAI1_RXD1,
+	PAD_SAI1_RXD2, PAD_SAI1_RXD3, PAD_SAI1_RXD4, PAD_SAI1_RXD5,
+	PAD_SAI1_RXD6, PAD_SAI1_RXD7, PAD_SAI1_TXFS, PAD_SAI1_TXC,
+	PAD_SAI1_TXD0, PAD_SAI1_TXD1, PAD_SAI1_TXD2, PAD_SAI1_TXD3,
+	PAD_SAI1_TXD4, PAD_SAI1_TXD5, PAD_SAI1_TXD6, PAD_SAI1_TXD7,
+	PAD_SAI1_MCLK,
+
+	PAD_SAI2_RXFS, PAD_SAI2_RXC, PAD_SAI2_RXD0, PAD_SAI2_TXFS,
+	PAD_SAI2_TXC, PAD_SAI2_TXD0, PAD_SAI2_MCLK,
+
+	PAD_SAI3_RXFS, PAD_SAI3_RXC, PAD_SAI3_RXD, PAD_SAI3_TXFS,
+	PAD_SAI3_TXC, PAD_SAI3_TXD, PAD_SAI3_MCLK,
+
+	PAD_SPDIF_TX, PAD_SPDIF_RX, PAD_SPDIF_EXT_CLK,
+
+	PAD_ECSPI1_SCLK, PAD_ECSPI1_MOSI, PAD_ECSPI1_MISO, PAD_ECSPI1_SS0,
+	PAD_ECSPI2_SCLK, PAD_ECSPI2_MOSI, PAD_ECSPI2_MISO, PAD_ECSPI2_SS0,
+
+	PAD_I2C1_SCL, PAD_I2C1_SDA,
+	PAD_I2C2_SCL, PAD_I2C2_SDA,
+	PAD_I2C3_SCL, PAD_I2C3_SDA,
+	PAD_I2C4_SCL, PAD_I2C4_SDA,
+
+	PAD_UART1_RXD, PAD_UART1_TXD,
+	PAD_UART2_RXD, PAD_UART2_TXD,
+	PAD_UART3_RXD, PAD_UART3_TXD,
+	PAD_UART4_RXD, PAD_UART4_TXD,
+};
+
+enum {
+	/* signals with input muxes (must be first for daisytab) */
+	CCM_PMIC_READY = 0,
+	ENET1_MDIO,
+	PCIE1_CLKREQ_B, PCIE2_CLKREQ_B,
+	SAI1_RX_BCLK, SAI1_RX_SYNC, SAI1_TX_SYNC,
+	SAI5_MCLK, SAI5_RXD0, SAI5_RXD1, SAI5_RXD2, SAI5_RXD3,
+	SAI5_RX_BCLK, SAI5_RX_SYNC, SAI5_TX_BLCK, SAI5_TX_SYNC,
+	SAI6_MCLK, SAI6_RXD0, SAI6_RX_BCLK, SAI6_RX_SYNC,
+	SAI6_TX_BCLK, SAY6_TX_SYNC,
+	UART1_RTS_B, UART1_RXD,
+	UART2_RTS_B, UART2_RXD,
+	UART3_RTS_B, UART3_RXD,
+	UART4_RTS_B, UART4_RXD,
+
+	/* signals without input muxes */
+	ANAMIX_REF_CLK_25M,
+	ANAMIX_REF_CLK_32K,
+	CCM_CLKO1,
+	CCM_CLKO2,
+	CCM_ENET_PHY_REF_CLK_ROOT,
+	CCM_EXT_CLK1,
+	CCM_EXT_CLK2,
+	CCM_EXT_CLK3,
+	CCM_EXT_CLK4,
+
+	CORESIGHT_EVENTI, CORESIGHT_EVENTO, CORESIGHT_TRACE0,
+	CORESIGHT_TRACE1, CORESIGHT_TRACE10, CORESIGHT_TRACE11,
+	CORESIGHT_TRACE12, CORESIGHT_TRACE13, CORESIGHT_TRACE14,
+	CORESIGHT_TRACE15, CORESIGHT_TRACE2, CORESIGHT_TRACE3,
+	CORESIGHT_TRACE4, CORESIGHT_TRACE5, CORESIGHT_TRACE6,
+	CORESIGHT_TRACE7, CORESIGHT_TRACE8, CORESIGHT_TRACE9,
+	CORESIGHT_TRACE_CLK, CORESIGHT_TRACE_CTL,
+
+	ECSPI1_MISO, ECSPI1_MOSI, ECSPI1_SCLK, ECSPI1_SS0,
+	ECSPI2_MISO, ECSPI2_MOSI, ECSPI2_SCLK, ECSPI2_SS0,
+	ECSPI3_MISO, ECSPI3_MOSI, ECSPI3_SCLK, ECSPI3_SS0,
+	ENET1_1588_EVENT0_IN, ENET1_1588_EVENT0_OUT,
+	ENET1_1588_EVENT1_IN, ENET1_1588_EVENT1_OUT,
+	ENET1_MDC, ENET1_RGMII_RD0, ENET1_RGMII_RD1, ENET1_RGMII_RD2,
+	ENET1_RGMII_RD3, ENET1_RGMII_RXC, ENET1_RGMII_RX_CTL,
+	ENET1_RGMII_TD0, ENET1_RGMII_TD1, ENET1_RGMII_TD2,
+	ENET1_RGMII_TD3, ENET1_RGMII_TXC, ENET1_RGMII_TX_CTL,
+	ENET1_RX_ER, ENET1_TX_CLK, ENET1_TX_ER,
+
+	GPIO1_IO00, GPIO1_IO01, GPIO1_IO02, GPIO1_IO03, GPIO1_IO04,
+	GPIO1_IO05, GPIO1_IO06, GPIO1_IO07, GPIO1_IO08, GPIO1_IO09,
+	GPIO1_IO10, GPIO1_IO11, GPIO1_IO12, GPIO1_IO13, GPIO1_IO14,
+	GPIO1_IO15, GPIO1_IO16, GPIO1_IO17, GPIO1_IO18, GPIO1_IO19,
+	GPIO1_IO20, GPIO1_IO21, GPIO1_IO22, GPIO1_IO23, GPIO1_IO24,
+	GPIO1_IO25, GPIO1_IO26, GPIO1_IO27, GPIO1_IO28, GPIO1_IO29,
+
+	GPIO2_IO00, GPIO2_IO01, GPIO2_IO02, GPIO2_IO03, GPIO2_IO04,
+	GPIO2_IO05, GPIO2_IO06, GPIO2_IO07, GPIO2_IO08, GPIO2_IO09,
+	GPIO2_IO10, GPIO2_IO11, GPIO2_IO12, GPIO2_IO13, GPIO2_IO14,
+	GPIO2_IO15, GPIO2_IO16, GPIO2_IO17, GPIO2_IO18, GPIO2_IO19,
+	GPIO2_IO20,
+
+	GPIO3_IO00, GPIO3_IO01, GPIO3_IO02, GPIO3_IO03, GPIO3_IO04,
+	GPIO3_IO05, GPIO3_IO06, GPIO3_IO07, GPIO3_IO08, GPIO3_IO09,
+	GPIO3_IO10, GPIO3_IO11, GPIO3_IO12, GPIO3_IO13, GPIO3_IO14,
+	GPIO3_IO15, GPIO3_IO16, GPIO3_IO17, GPIO3_IO18, GPIO3_IO19,
+	GPIO3_IO20, GPIO3_IO21, GPIO3_IO22, GPIO3_IO23, GPIO3_IO24,
+	GPIO3_IO25,
+
+	GPIO4_IO00, GPIO4_IO01, GPIO4_IO02, GPIO4_IO03, GPIO4_IO04,
+	GPIO4_IO05, GPIO4_IO06, GPIO4_IO07, GPIO4_IO08, GPIO4_IO09,
+	GPIO4_IO10, GPIO4_IO11, GPIO4_IO12, GPIO4_IO13, GPIO4_IO14,
+	GPIO4_IO15, GPIO4_IO16, GPIO4_IO17, GPIO4_IO18, GPIO4_IO19,
+	GPIO4_IO20, GPIO4_IO21, GPIO4_IO22, GPIO4_IO23, GPIO4_IO24,
+	GPIO4_IO25, GPIO4_IO26, GPIO4_IO27, GPIO4_IO28, GPIO4_IO29,
+	GPIO4_IO31,
+
+	GPIO5_IO00, GPIO5_IO01, GPIO5_IO02, GPIO5_IO03, GPIO5_IO04,
+	GPIO5_IO05, GPIO5_IO06, GPIO5_IO07, GPIO5_IO08, GPIO5_IO09,
+	GPIO5_IO10, GPIO5_IO11, GPIO5_IO12, GPIO5_IO13, GPIO5_IO14,
+	GPIO5_IO15, GPIO5_IO16, GPIO5_IO17, GPIO5_IO18, GPIO5_IO19,
+	GPIO5_IO20, GPIO5_IO21, GPIO5_IO22, GPIO5_IO23, GPIO5_IO24,
+	GPIO5_IO25, GPIO5_IO26, GPIO5_IO27, GPIO5_IO28, GPIO5_IO29,
+
+	GPT1_CAPTURE1, GPT1_CAPTURE2, GPT1_COMPARE1, GPT1_COMPARE2,
+	GPT1_COMPARE3, GPT1_CLK, GPT2_CLK, GPT3_CLK,
+
+	I2C1_SCL, I2C1_SDA,
+	I2C2_SCL, I2C2_SDA,
+	I2C3_SCL, I2C3_SDA,
+	I2C4_SCL, I2C4_SDA,
+	M4_NMI,
+	PCIE_CLKREQ_B,
+	PWM1_OUT, PWM2_OUT, PWM3_OUT, PWM4_OUT,
+
+	QSPI_A_DATA0, QSPI_A_DATA1, QSPI_A_DATA2, QSPI_A_DATA3,
+	QSPI_A_DQS, QSPI_A_SCLK, QSPI_A_SS0_B, QSPI_A_SS1_B,
+
+	QSPI_B_DATA0, QSPI_B_DATA1, QSPI_B_DATA2, QSPI_B_DATA3,
+	QSPI_B_DQS, QSPI_B_SCLK, QSPI_B_SS0_B, QSPI_B_SS1_B,
+
+	RAWNAND_ALE, RAWNAND_CE0_B, RAWNAND_CE1_B, RAWNAND_CE2_B,
+	RAWNAND_CE3_B, RAWNAND_CLE, RAWNAND_DATA00, RAWNAND_DATA01,
+	RAWNAND_DATA02, RAWNAND_DATA03, RANWNAD_DATA04,
+	RAWNAND_DATA05, RAWNAND_DATA06, RAWNAND_DATA07, RAWNAND_DQS,
+	RAWNAND_READY_B, RAWNAND_RE_B, RAWNAND_WE_B, RAWNAND_WP_B,
+
+	SAI1_MCLK, SAI1_RX_DATA0, SAI1_RX_DATA1, SAI1_RX_DATA2,
+	SAI1_RX_DATA3, SAI1_RX_DATA4, SAI1_RX_DATA5, SAI1_RX_DATA6,
+	SAI1_RX_DATA7, SAI1_TX_BCLK, SAI1_TX_DATA0, SAI1_TX_DATA1,
+	SAI1_TX_DATA2, SAI1_TX_DATA3, SAI1_TX_DATA4, SAI1_TX_DATA5,
+	SAI1_TX_DATA6, SAI1_TX_DATA7,
+
+	SAI2_MCLK, SAI2_RX_BCLK, SAI2_RX_DATA0, SAI2_RX_SYNC,
+	SAI2_TX_BCLK, SAI2_TX_DATA0, SAI2_TX_SYNC,
+	SAI3_MCLK, SAI3_RX_BCLK, SAI3_RX_DATA0, SAI3_RX_SYNC,
+	SAI3_TX_BCLK, SAI3_TX_DATA0, SAI3_TX_SYNC,
+
+	SAI4_MCLK,
+
+	SAI5_RX_DATA0, SAI5_RX_DATA1, SAI5_RX_DATA2, SAI5_RX_DATA3,
+	SAI5_TX_BCLK, SAI5_TX_DATA0, SAI5_TX_DATA1, SAI5_TX_DATA2,
+	SAI5_TX_DATA3,
+
+	SAI6_RC_BCLK, SAI6_RX_DATA0, SAI6_TX_DATA0, SAI6_TX_SYNC,
+
+	SDMA1_EXT_EVENT0, SDMA1_EXT_EVENT1,
+	SDMA2_EXT_EVENT0, SDMA2_EXT_EVENT1,
+
+	SJC_DE_B,
+
+	SPDIF1_EXT_CLK, SPDIF1_IN, SPDIF1_OUT,
+
+	SRC_BOOT_CFG0, SRC_BOOT_CFG1, SRC_BOOT_CFG2, SRC_BOOT_CFG3,
+	SRC_BOOT_CFG4, SRC_BOOT_CFG5, SRC_BOOT_CFG6, SRC_BOOT_CFG7,
+	SRC_BOOT_CFG8, SRC_BOOT_CFG9, SRC_BOOT_CFG10, SRC_BOOT_CFG11,
+	SRC_BOOT_CFG12, SRC_BOOT_CFG13, SRC_BOOT_CFG14, SRC_BOOT_CFG15,
+
+	UART1_CTS_B, UART1_RX, UART1_TX,
+	UART2_CTS_B, UART2_RX, UART2_TX,
+	UART3_CTS_B, UART3_RX, UART3_TX,
+	UART4_CTS_B, UART4_RX, UART4_TX,
+
+	USB1_OTG_ID, USB1_OTG_OC, USB1_OTG_PWR,
+	USB2_OTG_ID, USB2_OTG_OC, USB2_OTG_PWR,
+
+	USDHC1_CD_B, USDHC1_CLK, USDHC1_CMD, USDHC1_DATA0,
+	USDHC1_DATA1, USDHC1_DATA2, USDHC1_DATA3, USDHC1_DATA4,
+	USDHC1_DATA5, USDHC1_DATA6, USDHC1_DATA7, USDHC1_RESET_B,
+	USDHC1_STROBE, USDHC1_VSELECT, USDHC1_WP,
+
+	USDHC2_CD_B, USDHC2_CLK, USDHC2_CMD, USDHC2_DATA0,
+	USDHC2_DATA1, USDHC2_DATA2, USDHC2_DATA3, USDHC2_RESET_B,
+	USDHC2_VSELECT, USDHC2_WP,
+
+	WDOG1_WDOG_ANY, WDOG1_WDOG_B,
+};
+
+#define DAISY(x)	(0x8000|(((x)&7)<<12))
+#define DAISY_VAL(x)	(((x)>>12)&7)
+#define DAISY_ID(x)	((x) & ~DAISY(7))
+
+static ushort daisytab[] = {
+	[CCM_PMIC_READY]	0 | DAISY(1),
+	[ENET1_MDIO]		1 | DAISY(3),
+	[PCIE1_CLKREQ_B]	26 | DAISY(1),
+	[PCIE2_CLKREQ_B]	27 | DAISY(1),
+	[SAI1_RX_BCLK]		3 | DAISY(3),
+	[SAI1_RX_SYNC]		2 | DAISY(1),
+	[SAI1_TX_SYNC]		4 | DAISY(7),
+	[SAI5_MCLK]		28 | DAISY(3),
+	[SAI5_RXD0]		6 | DAISY(3),
+	[SAI5_RXD1]		7 | DAISY(3),
+	[SAI5_RXD2]		8 | DAISY(3),
+	[SAI5_RXD3]		9 | DAISY(3),
+	[SAI5_RX_BCLK]		5 | DAISY(3),
+	[SAI5_RX_SYNC]		10 | DAISY(3),
+	[SAI5_TX_BLCK]		11 | DAISY(3),
+	[SAI5_TX_SYNC]		12 | DAISY(3),
+	[SAI6_MCLK]		29 | DAISY(1),
+	[SAI6_RXD0]		22 | DAISY(1),
+	[SAI6_RX_BCLK]		21 | DAISY(1),
+	[SAI6_RX_SYNC]		23 | DAISY(1),
+	[SAI6_TX_BCLK]		24 | DAISY(1),
+	[SAY6_TX_SYNC]		25 | DAISY(1),
+	[UART1_RTS_B]		13 | DAISY(1),
+	[UART1_RXD]		14 | DAISY(1),
+	[UART2_RTS_B]		15 | DAISY(1),
+	[UART2_RXD]		16 | DAISY(1),
+	[UART3_RTS_B]		17 | DAISY(1),
+	[UART3_RXD]		18 | DAISY(3),
+	[UART4_RTS_B]		19 | DAISY(1),
+	[UART4_RXD]		20 | DAISY(3),
+};
+
+static ushort padmux[] = {
+	[PAD_GPIO1_IO00*8]	GPIO1_IO00, CCM_ENET_PHY_REF_CLK_ROOT, 0, 0, 0, ANAMIX_REF_CLK_32K, CCM_EXT_CLK1, 0, 
+	[PAD_GPIO1_IO01*8]	GPIO1_IO01, PWM1_OUT, 0, 0, 0, ANAMIX_REF_CLK_25M, CCM_EXT_CLK2, 0, 
+	[PAD_GPIO1_IO02*8]	GPIO1_IO02, WDOG1_WDOG_B, 0, 0, 0, WDOG1_WDOG_ANY, 0, SJC_DE_B, 
+	[PAD_GPIO1_IO03*8]	GPIO1_IO03, USDHC1_VSELECT, 0, 0, 0, SDMA1_EXT_EVENT0, 0, 0, 
+	[PAD_GPIO1_IO04*8]	GPIO1_IO04, USDHC2_VSELECT, 0, 0, 0, SDMA1_EXT_EVENT1, 0, 0, 
+	[PAD_GPIO1_IO05*8]	GPIO1_IO05, M4_NMI, 0, 0, 0, CCM_PMIC_READY|DAISY(0), 0, 0, 
+	[PAD_GPIO1_IO06*8]	GPIO1_IO06, ENET1_MDC, 0, 0, 0, USDHC1_CD_B, CCM_EXT_CLK3, 0, 
+	[PAD_GPIO1_IO07*8]	GPIO1_IO07, ENET1_MDIO|DAISY(0), 0, 0, 0, USDHC1_WP, CCM_EXT_CLK4, 0, 
+	[PAD_GPIO1_IO08*8]	GPIO1_IO08, ENET1_1588_EVENT0_IN, 0, 0, 0, USDHC2_RESET_B, 0, 0, 
+	[PAD_GPIO1_IO09*8]	GPIO1_IO09, ENET1_1588_EVENT0_OUT, 0, 0, 0, SDMA2_EXT_EVENT0, 0, 0, 
+	[PAD_GPIO1_IO10*8]	GPIO1_IO10, USB1_OTG_ID, 0, 0, 0, 0, 0, 0, 
+	[PAD_GPIO1_IO11*8]	GPIO1_IO11, USB2_OTG_ID, 0, 0, 0, CCM_PMIC_READY|DAISY(1), 0, 0, 
+	[PAD_GPIO1_IO12*8]	GPIO1_IO12, USB1_OTG_PWR, 0, 0, 0, SDMA2_EXT_EVENT1, 0, 0, 
+	[PAD_GPIO1_IO13*8]	GPIO1_IO13, USB1_OTG_OC, 0, 0, 0, PWM2_OUT, 0, 0, 
+	[PAD_GPIO1_IO14*8]	GPIO1_IO14, USB2_OTG_PWR, 0, 0, 0, PWM3_OUT, CCM_CLKO1, 0, 
+	[PAD_GPIO1_IO15*8]	GPIO1_IO15, USB2_OTG_OC, 0, 0, 0, PWM4_OUT, CCM_CLKO2, 0, 
+	[PAD_ENET_MDC*8]	ENET1_MDC, 0, 0, 0, 0, GPIO1_IO16, 0, 0, 
+	[PAD_ENET_MDIO*8]	ENET1_MDIO|DAISY(1), 0, 0, 0, 0, GPIO1_IO17, 0, 0, 
+	[PAD_ENET_TD3*8]	ENET1_RGMII_TD3, 0, 0, 0, 0, GPIO1_IO18, 0, 0, 
+	[PAD_ENET_TD2*8]	ENET1_RGMII_TD2, ENET1_TX_CLK, 0, 0, 0, GPIO1_IO19, 0, 0, 
+	[PAD_ENET_TD1*8]	ENET1_RGMII_TD1, 0, 0, 0, 0, GPIO1_IO20, 0, 0, 
+	[PAD_ENET_TD0*8]	ENET1_RGMII_TD0, 0, 0, 0, 0, GPIO1_IO21, 0, 0, 
+	[PAD_ENET_TX_CTL*8]	ENET1_RGMII_TX_CTL, 0, 0, 0, 0, GPIO1_IO22, 0, 0, 
+	[PAD_ENET_TXC*8]	ENET1_RGMII_TXC, ENET1_TX_ER, 0, 0, 0, GPIO1_IO23, 0, 0, 
+	[PAD_ENET_RX_CTL*8]	ENET1_RGMII_RX_CTL, 0, 0, 0, 0, GPIO1_IO24, 0, 0, 
+	[PAD_ENET_RXC*8]	ENET1_RGMII_RXC, ENET1_RX_ER, 0, 0, 0, GPIO1_IO25, 0, 0, 
+	[PAD_ENET_RD0*8]	ENET1_RGMII_RD0, 0, 0, 0, 0, GPIO1_IO26, 0, 0, 
+	[PAD_ENET_RD1*8]	ENET1_RGMII_RD1, 0, 0, 0, 0, GPIO1_IO27, 0, 0, 
+	[PAD_ENET_RD2*8]	ENET1_RGMII_RD2, 0, 0, 0, 0, GPIO1_IO28, 0, 0, 
+	[PAD_ENET_RD3*8]	ENET1_RGMII_RD3, 0, 0, 0, 0, GPIO1_IO29, 0, 0, 
+	[PAD_SD1_CLK*8]		USDHC1_CLK, 0, 0, 0, 0, GPIO2_IO00, 0, 0, 
+	[PAD_SD1_CMD*8]		USDHC1_CMD, 0, 0, 0, 0, GPIO2_IO01, 0, 0, 
+	[PAD_SD1_DATA0*8]	USDHC1_DATA0, 0, 0, 0, 0, GPIO2_IO02, 0, 0, 
+	[PAD_SD1_DATA1*8]	USDHC1_DATA1, 0, 0, 0, 0, GPIO2_IO03, 0, 0, 
+	[PAD_SD1_DATA2*8]	USDHC1_DATA2, 0, 0, 0, 0, GPIO2_IO04, 0, 0, 
+	[PAD_SD1_DATA3*8]	USDHC1_DATA3, 0, 0, 0, 0, GPIO2_IO05, 0, 0, 
+	[PAD_SD1_DATA4*8]	USDHC1_DATA4, 0, 0, 0, 0, GPIO2_IO06, 0, 0, 
+	[PAD_SD1_DATA5*8]	USDHC1_DATA5, 0, 0, 0, 0, GPIO2_IO07, 0, 0, 
+	[PAD_SD1_DATA6*8]	USDHC1_DATA6, 0, 0, 0, 0, GPIO2_IO08, 0, 0, 
+	[PAD_SD1_DATA7*8]	USDHC1_DATA7, 0, 0, 0, 0, GPIO2_IO09, 0, 0, 
+	[PAD_SD1_RESET_B*8]	USDHC1_RESET_B, 0, 0, 0, 0, GPIO2_IO10, 0, 0, 
+	[PAD_SD1_STROBE*8]	USDHC1_STROBE, 0, 0, 0, 0, GPIO2_IO11, 0, 0, 
+	[PAD_SD2_CD_B*8]	USDHC2_CD_B, 0, 0, 0, 0, GPIO2_IO12, 0, 0, 
+	[PAD_SD2_CLK*8]		USDHC2_CLK, 0, 0, 0, 0, GPIO2_IO13, 0, 0, 
+	[PAD_SD2_CMD*8]		USDHC2_CMD, 0, 0, 0, 0, GPIO2_IO14, 0, 0, 
+	[PAD_SD2_DATA0*8]	USDHC2_DATA0, 0, 0, 0, 0, GPIO2_IO15, 0, 0, 
+	[PAD_SD2_DATA1*8]	USDHC2_DATA1, 0, 0, 0, 0, GPIO2_IO16, 0, 0, 
+	[PAD_SD2_DATA2*8]	USDHC2_DATA2, 0, 0, 0, 0, GPIO2_IO17, 0, 0, 
+	[PAD_SD2_DATA3*8]	USDHC2_DATA3, 0, 0, 0, 0, GPIO2_IO18, 0, 0, 
+	[PAD_SD2_RESET_B*8]	USDHC2_RESET_B, 0, 0, 0, 0, GPIO2_IO19, 0, 0, 
+	[PAD_SD2_WP*8]		USDHC2_WP, 0, 0, 0, 0, GPIO2_IO20, 0, 0, 
+	[PAD_NAND_ALE*8]	RAWNAND_ALE, QSPI_A_SCLK, 0, 0, 0, GPIO3_IO00, 0, 0, 
+	[PAD_NAND_CE0_B*8]	RAWNAND_CE0_B, QSPI_A_SS0_B, 0, 0, 0, GPIO3_IO01, 0, 0, 
+	[PAD_NAND_CE1_B*8]	RAWNAND_CE1_B, QSPI_A_SS1_B, 0, 0, 0, GPIO3_IO02, 0, 0, 
+	[PAD_NAND_CE2_B*8]	RAWNAND_CE2_B, QSPI_B_SS0_B, 0, 0, 0, GPIO3_IO03, 0, 0, 
+	[PAD_NAND_CE3_B*8]	RAWNAND_CE3_B, QSPI_B_SS1_B, 0, 0, 0, GPIO3_IO04, 0, 0, 
+	[PAD_NAND_CLE*8]	RAWNAND_CLE, QSPI_B_SCLK, 0, 0, 0, GPIO3_IO05, 0, 0, 
+	[PAD_NAND_DATA0*8]	RAWNAND_DATA00, QSPI_A_DATA0, 0, 0, 0, GPIO3_IO06, 0, 0, 
+	[PAD_NAND_DATA1*8]	RAWNAND_DATA01, QSPI_A_DATA1, 0, 0, 0, GPIO3_IO07, 0, 0, 
+	[PAD_NAND_DATA2*8]	RAWNAND_DATA02, QSPI_A_DATA2, 0, 0, 0, GPIO3_IO08, 0, 0, 
+	[PAD_NAND_DATA3*8]	RAWNAND_DATA03, QSPI_A_DATA3, 0, 0, 0, GPIO3_IO09, 0, 0, 
+	[PAD_NAND_DATA4*8]	RANWNAD_DATA04, QSPI_B_DATA0, 0, 0, 0, GPIO3_IO10, 0, 0, 
+	[PAD_NAND_DATA5*8]	RAWNAND_DATA05, QSPI_B_DATA1, 0, 0, 0, GPIO3_IO11, 0, 0, 
+	[PAD_NAND_DATA6*8]	RAWNAND_DATA06, QSPI_B_DATA2, 0, 0, 0, GPIO3_IO12, 0, 0, 
+	[PAD_NAND_DATA7*8]	RAWNAND_DATA07, QSPI_B_DATA3, 0, 0, 0, GPIO3_IO13, 0, 0, 
+	[PAD_NAND_DQS*8]	RAWNAND_DQS, QSPI_A_DQS, 0, 0, 0, GPIO3_IO14, 0, 0, 
+	[PAD_NAND_RE_B*8]	RAWNAND_RE_B, QSPI_B_DQS, 0, 0, 0, GPIO3_IO15, 0, 0, 
+	[PAD_NAND_READY_B*8]	RAWNAND_READY_B, 0, 0, 0, 0, GPIO3_IO16, 0, 0, 
+	[PAD_NAND_WE_B*8]	RAWNAND_WE_B, 0, 0, 0, 0, GPIO3_IO17, 0, 0, 
+	[PAD_NAND_WP_B*8]	RAWNAND_WP_B, 0, 0, 0, 0, GPIO3_IO18, 0, 0, 
+	[PAD_SAI5_RXFS*8]	SAI5_RX_SYNC|DAISY(0), SAI1_TX_DATA0, 0, 0, 0, GPIO3_IO19, 0, 0, 
+	[PAD_SAI5_RXC*8]	SAI5_RX_BCLK|DAISY(0), SAI1_TX_DATA1, 0, 0, 0, GPIO3_IO20, 0, 0, 
+	[PAD_SAI5_RXD0*8]	SAI5_RX_DATA0, SAI1_TX_DATA2, 0, 0, 0, GPIO3_IO21, 0, 0, 
+	[PAD_SAI5_RXD1*8]	SAI5_RX_DATA1, SAI1_TX_DATA3, SAI1_TX_SYNC|DAISY(0), SAI5_TX_SYNC|DAISY(0), 0, GPIO3_IO22, 0, 0, 
+	[PAD_SAI5_RXD2*8]	SAI5_RX_DATA2, SAI1_TX_DATA4, SAI1_TX_SYNC|DAISY(1), SAI5_TX_BCLK, 0, GPIO3_IO23, 0, 0, 
+	[PAD_SAI5_RXD3*8]	SAI5_RX_DATA3, SAI1_TX_DATA5, 0, SAI5_TX_DATA0, 0, GPIO3_IO24, 0, 0, 
+	[PAD_SAI5_MCLK*8]	SAI5_MCLK|DAISY(0), SAI1_TX_BCLK, SAI4_MCLK, 0, 0, GPIO3_IO25, 0, 0, 
+	[PAD_SAI1_RXFS*8]	SAI1_RX_SYNC|DAISY(0), SAI5_RX_SYNC|DAISY(1), 0, 0, CORESIGHT_TRACE_CLK, GPIO4_IO00, 0, 0, 
+	[PAD_SAI1_RXC*8]	SAI1_RX_BCLK, SAI5_RX_BCLK|DAISY(1), 0, 0, CORESIGHT_TRACE_CTL, GPIO4_IO01, 0, 0, 
+	[PAD_SAI1_RXD0*8]	SAI1_RX_DATA0, SAI5_RX_DATA0, 0, 0, CORESIGHT_TRACE0, GPIO4_IO02, SRC_BOOT_CFG0, 0, 
+	[PAD_SAI1_RXD1*8]	SAI1_RX_DATA1, SAI5_RX_DATA1, 0, 0, CORESIGHT_TRACE1, GPIO4_IO03, SRC_BOOT_CFG1, 0, 
+	[PAD_SAI1_RXD2*8]	SAI1_RX_DATA2, SAI5_RX_DATA2, 0, 0, CORESIGHT_TRACE2, GPIO4_IO04, SRC_BOOT_CFG2, 0, 
+	[PAD_SAI1_RXD3*8]	SAI1_RX_DATA3, SAI5_RX_DATA3, 0, 0, CORESIGHT_TRACE3, GPIO4_IO05, SRC_BOOT_CFG3, 0, 
+	[PAD_SAI1_RXD4*8]	SAI1_RX_DATA4, SAI6_TX_BCLK|DAISY(0), SAI6_RX_BCLK|DAISY(0), 0, CORESIGHT_TRACE4, GPIO4_IO06, SRC_BOOT_CFG4, 0, 
+	[PAD_SAI1_RXD5*8]	SAI1_RX_DATA5, SAI6_TX_DATA0, SAI6_RX_DATA0, SAI1_RX_SYNC|DAISY(1), CORESIGHT_TRACE5, GPIO4_IO07, SRC_BOOT_CFG5, 0, 
+	[PAD_SAI1_RXD6*8]	SAI1_RX_DATA6, SAI6_TX_SYNC, SAI6_RX_SYNC|DAISY(0), 0, CORESIGHT_TRACE6, GPIO4_IO08, SRC_BOOT_CFG6, 0, 
+	[PAD_SAI1_RXD7*8]	SAI1_RX_DATA7, SAI6_MCLK|DAISY(0), SAI1_TX_SYNC|DAISY(4), SAI1_TX_DATA4, CORESIGHT_TRACE7, GPIO4_IO09, SRC_BOOT_CFG7, 0, 
+	[PAD_SAI1_TXFS*8]	SAI1_TX_SYNC|DAISY(3), SAI5_TX_SYNC|DAISY(1), 0, 0, CORESIGHT_EVENTO, GPIO4_IO10, 0, 0, 
+	[PAD_SAI1_TXC*8]	SAI1_TX_BCLK, SAI5_TX_BCLK, 0, 0, CORESIGHT_EVENTI, GPIO4_IO11, 0, 0, 
+	[PAD_SAI1_TXD0*8]	SAI1_TX_DATA0, SAI5_TX_DATA0, 0, 0, CORESIGHT_TRACE8, GPIO4_IO12, SRC_BOOT_CFG8, 0, 
+	[PAD_SAI1_TXD1*8]	SAI1_TX_DATA1, SAI5_TX_DATA1, 0, 0, CORESIGHT_TRACE9, GPIO4_IO13, SRC_BOOT_CFG9, 0, 
+	[PAD_SAI1_TXD2*8]	SAI1_TX_DATA2, SAI5_TX_DATA2, 0, 0, CORESIGHT_TRACE10, GPIO4_IO14, SRC_BOOT_CFG10, 0, 
+	[PAD_SAI1_TXD3*8]	SAI1_TX_DATA3, SAI5_TX_DATA3, 0, 0, CORESIGHT_TRACE11, GPIO4_IO15, SRC_BOOT_CFG11, 0, 
+	[PAD_SAI1_TXD4*8]	SAI1_TX_DATA4, SAI6_RC_BCLK, SAI6_TX_BCLK|DAISY(1), 0, CORESIGHT_TRACE12, GPIO4_IO16, SRC_BOOT_CFG12, 0, 
+	[PAD_SAI1_TXD5*8]	SAI1_TX_DATA5, SAI6_RX_DATA0, SAI6_TX_DATA0, 0, CORESIGHT_TRACE13, GPIO4_IO17, SRC_BOOT_CFG13, 0, 
+	[PAD_SAI1_TXD6*8]	SAI1_TX_DATA6, SAI6_RX_SYNC|DAISY(1), SAI6_TX_SYNC, 0, CORESIGHT_TRACE14, GPIO4_IO18, SRC_BOOT_CFG14, 0, 
+	[PAD_SAI1_TXD7*8]	SAI1_TX_DATA7, SAI6_MCLK|DAISY(1), 0, 0, CORESIGHT_TRACE15, GPIO4_IO19, SRC_BOOT_CFG15, 0, 
+	[PAD_SAI1_MCLK*8]	SAI1_MCLK, SAI5_MCLK|DAISY(1), SAI1_TX_BCLK, 0, 0, GPIO4_IO20, 0, 0, 
+	[PAD_SAI2_RXFS*8]	SAI2_RX_SYNC, SAI5_TX_SYNC|DAISY(2), 0, 0, 0, GPIO4_IO21, 0, 0, 
+	[PAD_SAI2_RXC*8]	SAI2_RX_BCLK, SAI5_TX_BCLK, 0, 0, 0, GPIO4_IO22, 0, 0, 
+	[PAD_SAI2_RXD0*8]	SAI2_RX_DATA0, SAI5_TX_DATA0, 0, 0, 0, GPIO4_IO23, 0, 0, 
+	[PAD_SAI2_TXFS*8]	SAI2_TX_SYNC, SAI5_TX_DATA1, 0, 0, 0, GPIO4_IO24, 0, 0, 
+	[PAD_SAI2_TXC*8]	SAI2_TX_BCLK, SAI5_TX_DATA2, 0, 0, 0, GPIO4_IO25, 0, 0, 
+	[PAD_SAI2_TXD0*8]	SAI2_TX_DATA0, SAI5_TX_DATA3, 0, 0, 0, GPIO4_IO26, 0, 0, 
+	[PAD_SAI2_MCLK*8]	SAI2_MCLK, SAI5_MCLK|DAISY(2), 0, 0, 0, GPIO4_IO27, 0, 0, 
+	[PAD_SAI3_RXFS*8]	SAI3_RX_SYNC, GPT1_CAPTURE1, SAI5_RX_SYNC|DAISY(2), 0, 0, GPIO4_IO28, 0, 0, 
+	[PAD_SAI3_RXC*8]	SAI3_RX_BCLK, GPT1_CAPTURE2, SAI5_RX_BCLK|DAISY(2), 0, 0, GPIO4_IO29, 0, 0, 
+	[PAD_SAI3_RXD*8]	SAI3_RX_DATA0, GPT1_COMPARE1, 0, 0, 0, 0, 0, 0, 
+	[PAD_SAI3_TXFS*8]	SAI3_TX_SYNC, GPT1_CLK, SAI5_RX_DATA1, 0, 0, GPIO4_IO31, 0, 0, 
+	[PAD_SAI3_TXC*8]	SAI3_TX_BCLK, GPT1_COMPARE2, SAI5_RX_DATA2, 0, 0, GPIO5_IO00, 0, 0, 
+	[PAD_SAI3_TXD*8]	SAI3_TX_DATA0, GPT1_COMPARE3, SAI5_RX_DATA3, 0, 0, GPIO5_IO01, 0, 0, 
+	[PAD_SAI3_MCLK*8]	SAI3_MCLK, PWM4_OUT, SAI5_MCLK|DAISY(3), 0, 0, GPIO5_IO02, 0, 0, 
+	[PAD_SPDIF_TX*8]	SPDIF1_OUT, PWM3_OUT, 0, 0, 0, GPIO5_IO03, 0, 0, 
+	[PAD_SPDIF_RX*8]	SPDIF1_IN, PWM2_OUT, 0, 0, 0, GPIO5_IO04, 0, 0, 
+	[PAD_SPDIF_EXT_CLK*8]	SPDIF1_EXT_CLK, PWM1_OUT, 0, 0, 0, GPIO5_IO05, 0, 0, 
+	[PAD_ECSPI1_SCLK*8]	ECSPI1_SCLK, UART3_RX, 0, 0, 0, GPIO5_IO06, 0, 0, 
+	[PAD_ECSPI1_MOSI*8]	ECSPI1_MOSI, UART3_TX, 0, 0, 0, GPIO5_IO07, 0, 0, 
+	[PAD_ECSPI1_MISO*8]	ECSPI1_MISO, UART3_CTS_B, 0, 0, 0, GPIO5_IO08, 0, 0, 
+	[PAD_ECSPI1_SS0*8]	ECSPI1_SS0, UART3_RTS_B|DAISY(1), 0, 0, 0, GPIO5_IO09, 0, 0, 
+	[PAD_ECSPI2_SCLK*8]	ECSPI2_SCLK, UART4_RX, 0, 0, 0, GPIO5_IO10, 0, 0, 
+	[PAD_ECSPI2_MOSI*8]	ECSPI2_MOSI, UART4_TX, 0, 0, 0, GPIO5_IO11, 0, 0, 
+	[PAD_ECSPI2_MISO*8]	ECSPI2_MISO, UART4_CTS_B, 0, 0, 0, GPIO5_IO12, 0, 0, 
+	[PAD_ECSPI2_SS0*8]	ECSPI2_SS0, UART4_RTS_B|DAISY(1), 0, 0, 0, GPIO5_IO13, 0, 0, 
+	[PAD_I2C1_SCL*8]	I2C1_SCL, ENET1_MDC, 0, 0, 0, GPIO5_IO14, 0, 0, 
+	[PAD_I2C1_SDA*8]	I2C1_SDA, ENET1_MDIO|DAISY(2), 0, 0, 0, GPIO5_IO15, 0, 0, 
+	[PAD_I2C2_SCL*8]	I2C2_SCL, ENET1_1588_EVENT1_IN, 0, 0, 0, GPIO5_IO16, 0, 0, 
+	[PAD_I2C2_SDA*8]	I2C2_SDA, ENET1_1588_EVENT1_OUT, 0, 0, 0, GPIO5_IO17, 0, 0, 
+	[PAD_I2C3_SCL*8]	I2C3_SCL, PWM4_OUT, GPT2_CLK, 0, 0, GPIO5_IO18, 0, 0, 
+	[PAD_I2C3_SDA*8]	I2C3_SDA, PWM3_OUT, GPT3_CLK, 0, 0, GPIO5_IO19, 0, 0, 
+	[PAD_I2C4_SCL*8]	I2C4_SCL, PWM2_OUT, PCIE_CLKREQ_B, 0, 0, GPIO5_IO20, 0, 0, 
+	[PAD_I2C4_SDA*8]	I2C4_SDA, PWM1_OUT, PCIE2_CLKREQ_B|DAISY(0), 0, 0, GPIO5_IO21, 0, 0, 
+	[PAD_UART1_RXD*8]	UART1_RX, ECSPI3_SCLK, 0, 0, 0, GPIO5_IO22, 0, 0, 
+	[PAD_UART1_TXD*8]	UART1_TX, ECSPI3_MOSI, 0, 0, 0, GPIO5_IO23, 0, 0, 
+	[PAD_UART2_RXD*8]	UART2_RX, ECSPI3_MISO, 0, 0, 0, GPIO5_IO24, 0, 0, 
+	[PAD_UART2_TXD*8]	UART2_TX, ECSPI3_SS0, 0, 0, 0, GPIO5_IO25, 0, 0, 
+	[PAD_UART3_RXD*8]	UART3_RX, UART1_CTS_B, 0, 0, 0, GPIO5_IO26, 0, 0, 
+	[PAD_UART3_TXD*8]	UART3_TX, UART1_RTS_B|DAISY(1), 0, 0, 0, GPIO5_IO27, 0, 0, 
+	[PAD_UART4_RXD*8]	UART4_RX, UART2_CTS_B, PCIE1_CLKREQ_B|DAISY(1), 0, 0, GPIO5_IO28, 0, 0, 
+	[PAD_UART4_TXD*8]	UART4_TX, UART2_RTS_B|DAISY(1), PCIE2_CLKREQ_B|DAISY(1), 0, 0, GPIO5_IO29, 0, 0, 
+};
+
+static char *padname[] = {
+	[PAD_TEST_MODE]		"pad_test_mode",
+	[PAD_BOOT_MODE0]	"pad_boot_mode0",
+	[PAD_BOOT_MODE1]	"pad_boot_mode1",
+	[PAD_JTAG_MOD]		"pad_jtag_mod",
+	[PAD_JTAG_TRST_B]	"pad_jtag_trst_b",
+	[PAD_JTAG_TDI]		"pad_jtag_tdi",
+	[PAD_JTAG_TMS]		"pad_jtag_tms",
+	[PAD_JTAG_TCK]		"pad_jtag_tck",
+	[PAD_JTAG_TDO]		"pad_jtag_tdo",
+	[PAD_RTC]		"pad_rtc",
+	[PAD_PMIC_STBY_REQ]	"pad_pmic_stby_req",
+	[PAD_PMIC_ON_REQ]	"pad_pmic_on_req",
+	[PAD_ONOFF]		"pad_onoff",
+	[PAD_POR_B]		"pad_por_b",
+	[PAD_RTC_RESET_B]	"pad_rtc_reset_b",
+	[PAD_GPIO1_IO00]	"pad_gpio1_io00",
+	[PAD_GPIO1_IO01]	"pad_gpio1_io01",
+	[PAD_GPIO1_IO02]	"pad_gpio1_io02",
+	[PAD_GPIO1_IO03]	"pad_gpio1_io03",
+	[PAD_GPIO1_IO04]	"pad_gpio1_io04",
+	[PAD_GPIO1_IO05]	"pad_gpio1_io05",
+	[PAD_GPIO1_IO06]	"pad_gpio1_io06",
+	[PAD_GPIO1_IO07]	"pad_gpio1_io07",
+	[PAD_GPIO1_IO08]	"pad_gpio1_io08",
+	[PAD_GPIO1_IO09]	"pad_gpio1_io09",
+	[PAD_GPIO1_IO10]	"pad_gpio1_io10",
+	[PAD_GPIO1_IO11]	"pad_gpio1_io11",
+	[PAD_GPIO1_IO12]	"pad_gpio1_io12",
+	[PAD_GPIO1_IO13]	"pad_gpio1_io13",
+	[PAD_GPIO1_IO14]	"pad_gpio1_io14",
+	[PAD_GPIO1_IO15]	"pad_gpio1_io15",
+	[PAD_ENET_MDC]		"pad_enet_mdc",
+	[PAD_ENET_MDIO]		"pad_enet_mdio",
+	[PAD_ENET_TD3]		"pad_enet_td3",
+	[PAD_ENET_TD2]		"pad_enet_td2",
+	[PAD_ENET_TD1]		"pad_enet_td1",
+	[PAD_ENET_TD0]		"pad_enet_td0",
+	[PAD_ENET_TX_CTL]	"pad_enet_tx_ctl",
+	[PAD_ENET_TXC]		"pad_enet_txc",
+	[PAD_ENET_RX_CTL]	"pad_enet_rx_ctl",
+	[PAD_ENET_RXC]		"pad_enet_rxc",
+	[PAD_ENET_RD0]		"pad_enet_rd0",
+	[PAD_ENET_RD1]		"pad_enet_rd1",
+	[PAD_ENET_RD2]		"pad_enet_rd2",
+	[PAD_ENET_RD3]		"pad_enet_rd3",
+	[PAD_SD1_CLK]		"pad_sd1_clk",
+	[PAD_SD1_CMD]		"pad_sd1_cmd",
+	[PAD_SD1_DATA0]		"pad_sd1_data0",
+	[PAD_SD1_DATA1]		"pad_sd1_data1",
+	[PAD_SD1_DATA2]		"pad_sd1_data2",
+	[PAD_SD1_DATA3]		"pad_sd1_data3",
+	[PAD_SD1_DATA4]		"pad_sd1_data4",
+	[PAD_SD1_DATA5]		"pad_sd1_data5",
+	[PAD_SD1_DATA6]		"pad_sd1_data6",
+	[PAD_SD1_DATA7]		"pad_sd1_data7",
+	[PAD_SD1_RESET_B]	"pad_sd1_reset_b",
+	[PAD_SD1_STROBE]	"pad_sd1_strobe",
+	[PAD_SD2_CD_B]		"pad_sd2_cd_b",
+	[PAD_SD2_CLK]		"pad_sd2_clk",
+	[PAD_SD2_CMD]		"pad_sd2_cmd",
+	[PAD_SD2_DATA0]		"pad_sd2_data0",
+	[PAD_SD2_DATA1]		"pad_sd2_data1",
+	[PAD_SD2_DATA2]		"pad_sd2_data2",
+	[PAD_SD2_DATA3]		"pad_sd2_data3",
+	[PAD_SD2_RESET_B]	"pad_sd2_reset_b",
+	[PAD_SD2_WP]		"pad_sd2_wp",
+	[PAD_NAND_ALE]		"pad_nand_ale",
+	[PAD_NAND_CE0_B]	"pad_nand_ce0_b",
+	[PAD_NAND_CE1_B]	"pad_nand_ce1_b",
+	[PAD_NAND_CE2_B]	"pad_nand_ce2_b",
+	[PAD_NAND_CE3_B]	"pad_nand_ce3_b",
+	[PAD_NAND_CLE]		"pad_nand_cle",
+	[PAD_NAND_DATA0]	"pad_nand_data0",
+	[PAD_NAND_DATA1]	"pad_nand_data1",
+	[PAD_NAND_DATA2]	"pad_nand_data2",
+	[PAD_NAND_DATA3]	"pad_nand_data3",
+	[PAD_NAND_DATA4]	"pad_nand_data4",
+	[PAD_NAND_DATA5]	"pad_nand_data5",
+	[PAD_NAND_DATA6]	"pad_nand_data6",
+	[PAD_NAND_DATA7]	"pad_nand_data7",
+	[PAD_NAND_DQS]		"pad_nand_dqs",
+	[PAD_NAND_RE_B]		"pad_nand_re_b",
+	[PAD_NAND_READY_B]	"pad_nand_ready_b",
+	[PAD_NAND_WE_B]		"pad_nand_we_b",
+	[PAD_NAND_WP_B]		"pad_nand_wp_b",
+	[PAD_SAI5_RXFS]		"pad_sai5_rxfs",
+	[PAD_SAI5_RXC]		"pad_sai5_rxc",
+	[PAD_SAI5_RXD0]		"pad_sai5_rxd0",
+	[PAD_SAI5_RXD1]		"pad_sai5_rxd1",
+	[PAD_SAI5_RXD2]		"pad_sai5_rxd2",
+	[PAD_SAI5_RXD3]		"pad_sai5_rxd3",
+	[PAD_SAI5_MCLK]		"pad_sai5_mclk",
+	[PAD_SAI1_RXFS]		"pad_sai1_rxfs",
+	[PAD_SAI1_RXC]		"pad_sai1_rxc",
+	[PAD_SAI1_RXD0]		"pad_sai1_rxd0",
+	[PAD_SAI1_RXD1]		"pad_sai1_rxd1",
+	[PAD_SAI1_RXD2]		"pad_sai1_rxd2",
+	[PAD_SAI1_RXD3]		"pad_sai1_rxd3",
+	[PAD_SAI1_RXD4]		"pad_sai1_rxd4",
+	[PAD_SAI1_RXD5]		"pad_sai1_rxd5",
+	[PAD_SAI1_RXD6]		"pad_sai1_rxd6",
+	[PAD_SAI1_RXD7]		"pad_sai1_rxd7",
+	[PAD_SAI1_TXFS]		"pad_sai1_txfs",
+	[PAD_SAI1_TXC]		"pad_sai1_txc",
+	[PAD_SAI1_TXD0]		"pad_sai1_txd0",
+	[PAD_SAI1_TXD1]		"pad_sai1_txd1",
+	[PAD_SAI1_TXD2]		"pad_sai1_txd2",
+	[PAD_SAI1_TXD3]		"pad_sai1_txd3",
+	[PAD_SAI1_TXD4]		"pad_sai1_txd4",
+	[PAD_SAI1_TXD5]		"pad_sai1_txd5",
+	[PAD_SAI1_TXD6]		"pad_sai1_txd6",
+	[PAD_SAI1_TXD7]		"pad_sai1_txd7",
+	[PAD_SAI1_MCLK]		"pad_sai1_mclk",
+	[PAD_SAI2_RXFS]		"pad_sai2_rxfs",
+	[PAD_SAI2_RXC]		"pad_sai2_rxc",
+	[PAD_SAI2_RXD0]		"pad_sai2_rxd0",
+	[PAD_SAI2_TXFS]		"pad_sai2_txfs",
+	[PAD_SAI2_TXC]		"pad_sai2_txc",
+	[PAD_SAI2_TXD0]		"pad_sai2_txd0",
+	[PAD_SAI2_MCLK]		"pad_sai2_mclk",
+	[PAD_SAI3_RXFS]		"pad_sai3_rxfs",
+	[PAD_SAI3_RXC]		"pad_sai3_rxc",
+	[PAD_SAI3_RXD]		"pad_sai3_rxd",
+	[PAD_SAI3_TXFS]		"pad_sai3_txfs",
+	[PAD_SAI3_TXC]		"pad_sai3_txc",
+	[PAD_SAI3_TXD]		"pad_sai3_txd",
+	[PAD_SAI3_MCLK]		"pad_sai3_mclk",
+	[PAD_SPDIF_TX]		"pad_spdif_tx",
+	[PAD_SPDIF_RX]		"pad_spdif_rx",
+	[PAD_SPDIF_EXT_CLK]	"pad_spdif_ext_clk",
+	[PAD_ECSPI1_SCLK]	"pad_ecspi1_sclk",
+	[PAD_ECSPI1_MOSI]	"pad_ecspi1_mosi",
+	[PAD_ECSPI1_MISO]	"pad_ecspi1_miso",
+	[PAD_ECSPI1_SS0]	"pad_ecspi1_ss0",
+	[PAD_ECSPI2_SCLK]	"pad_ecspi2_sclk",
+	[PAD_ECSPI2_MOSI]	"pad_ecspi2_mosi",
+	[PAD_ECSPI2_MISO]	"pad_ecspi2_miso",
+	[PAD_ECSPI2_SS0]	"pad_ecspi2_ss0",
+	[PAD_I2C1_SCL]		"pad_i2c1_scl",
+	[PAD_I2C1_SDA]		"pad_i2c1_sda",
+	[PAD_I2C2_SCL]		"pad_i2c2_scl",
+	[PAD_I2C2_SDA]		"pad_i2c2_sda",
+	[PAD_I2C3_SCL]		"pad_i2c3_scl",
+	[PAD_I2C3_SDA]		"pad_i2c3_sda",
+	[PAD_I2C4_SCL]		"pad_i2c4_scl",
+	[PAD_I2C4_SDA]		"pad_i2c4_sda",
+	[PAD_UART1_RXD]		"pad_uart1_rxd",
+	[PAD_UART1_TXD]		"pad_uart1_txd",
+	[PAD_UART2_RXD]		"pad_uart2_rxd",
+	[PAD_UART2_TXD]		"pad_uart2_txd",
+	[PAD_UART3_RXD]		"pad_uart3_rxd",
+	[PAD_UART3_TXD]		"pad_uart3_txd",
+	[PAD_UART4_RXD]		"pad_uart4_rxd",
+	[PAD_UART4_TXD]		"pad_uart4_txd",
+};
+
+static char *signame[] = {
+	[CCM_PMIC_READY] "ccm_pmic_ready",
+	[ENET1_MDIO] "enet1_mdio",
+	[PCIE1_CLKREQ_B] "pcie1_clkreq_b",
+	[PCIE2_CLKREQ_B] "pcie2_clkreq_b",
+	[SAI1_RX_BCLK] "sai1_rx_bclk",
+	[SAI1_RX_SYNC] "sai1_rx_sync",
+	[SAI1_TX_SYNC] "sai1_tx_sync",
+	[SAI5_MCLK] "sai5_mclk",
+	[SAI5_RXD0] "sai5_rxd0",
+	[SAI5_RXD1] "sai5_rxd1",
+	[SAI5_RXD2] "sai5_rxd2",
+	[SAI5_RXD3] "sai5_rxd3",
+	[SAI5_RX_BCLK] "sai5_rx_bclk",
+	[SAI5_RX_SYNC] "sai5_rx_sync",
+	[SAI5_TX_BLCK] "sai5_tx_blck",
+	[SAI5_TX_SYNC] "sai5_tx_sync",
+	[SAI6_MCLK] "sai6_mclk",
+	[SAI6_RXD0] "sai6_rxd0",
+	[SAI6_RX_BCLK] "sai6_rx_bclk",
+	[SAI6_RX_SYNC] "sai6_rx_sync",
+	[SAI6_TX_BCLK] "sai6_tx_bclk",
+	[SAY6_TX_SYNC] "say6_tx_sync",
+	[UART1_RTS_B] "uart1_rts_b",
+	[UART1_RXD] "uart1_rxd",
+	[UART2_RTS_B] "uart2_rts_b",
+	[UART2_RXD] "uart2_rxd",
+	[UART3_RTS_B] "uart3_rts_b",
+	[UART3_RXD] "uart3_rxd",
+	[UART4_RTS_B] "uart4_rts_b",
+	[UART4_RXD] "uart4_rxd",
+	[ANAMIX_REF_CLK_25M] "anamix_ref_clk_25m",
+	[ANAMIX_REF_CLK_32K] "anamix_ref_clk_32k",
+	[CCM_CLKO1] "ccm_clko1",
+	[CCM_CLKO2] "ccm_clko2",
+	[CCM_ENET_PHY_REF_CLK_ROOT] "ccm_enet_phy_ref_clk_root",
+	[CCM_EXT_CLK1] "ccm_ext_clk1",
+	[CCM_EXT_CLK2] "ccm_ext_clk2",
+	[CCM_EXT_CLK3] "ccm_ext_clk3",
+	[CCM_EXT_CLK4] "ccm_ext_clk4",
+	[CORESIGHT_EVENTI] "coresight_eventi",
+	[CORESIGHT_EVENTO] "coresight_evento",
+	[CORESIGHT_TRACE0] "coresight_trace0",
+	[CORESIGHT_TRACE1] "coresight_trace1",
+	[CORESIGHT_TRACE10] "coresight_trace10",
+	[CORESIGHT_TRACE11] "coresight_trace11",
+	[CORESIGHT_TRACE12] "coresight_trace12",
+	[CORESIGHT_TRACE13] "coresight_trace13",
+	[CORESIGHT_TRACE14] "coresight_trace14",
+	[CORESIGHT_TRACE15] "coresight_trace15",
+	[CORESIGHT_TRACE2] "coresight_trace2",
+	[CORESIGHT_TRACE3] "coresight_trace3",
+	[CORESIGHT_TRACE4] "coresight_trace4",
+	[CORESIGHT_TRACE5] "coresight_trace5",
+	[CORESIGHT_TRACE6] "coresight_trace6",
+	[CORESIGHT_TRACE7] "coresight_trace7",
+	[CORESIGHT_TRACE8] "coresight_trace8",
+	[CORESIGHT_TRACE9] "coresight_trace9",
+	[CORESIGHT_TRACE_CLK] "coresight_trace_clk",
+	[CORESIGHT_TRACE_CTL] "coresight_trace_ctl",
+	[ECSPI1_MISO] "ecspi1_miso",
+	[ECSPI1_MOSI] "ecspi1_mosi",
+	[ECSPI1_SCLK] "ecspi1_sclk",
+	[ECSPI1_SS0] "ecspi1_ss0",
+	[ECSPI2_MISO] "ecspi2_miso",
+	[ECSPI2_MOSI] "ecspi2_mosi",
+	[ECSPI2_SCLK] "ecspi2_sclk",
+	[ECSPI2_SS0] "ecspi2_ss0",
+	[ECSPI3_MISO] "ecspi3_miso",
+	[ECSPI3_MOSI] "ecspi3_mosi",
+	[ECSPI3_SCLK] "ecspi3_sclk",
+	[ECSPI3_SS0] "ecspi3_ss0",
+	[ENET1_1588_EVENT0_IN] "enet1_1588_event0_in",
+	[ENET1_1588_EVENT0_OUT] "enet1_1588_event0_out",
+	[ENET1_1588_EVENT1_IN] "enet1_1588_event1_in",
+	[ENET1_1588_EVENT1_OUT] "enet1_1588_event1_out",
+	[ENET1_MDC] "enet1_mdc",
+	[ENET1_RGMII_RD0] "enet1_rgmii_rd0",
+	[ENET1_RGMII_RD1] "enet1_rgmii_rd1",
+	[ENET1_RGMII_RD2] "enet1_rgmii_rd2",
+	[ENET1_RGMII_RD3] "enet1_rgmii_rd3",
+	[ENET1_RGMII_RXC] "enet1_rgmii_rxc",
+	[ENET1_RGMII_RX_CTL] "enet1_rgmii_rx_ctl",
+	[ENET1_RGMII_TD0] "enet1_rgmii_td0",
+	[ENET1_RGMII_TD1] "enet1_rgmii_td1",
+	[ENET1_RGMII_TD2] "enet1_rgmii_td2",
+	[ENET1_RGMII_TD3] "enet1_rgmii_td3",
+	[ENET1_RGMII_TXC] "enet1_rgmii_txc",
+	[ENET1_RGMII_TX_CTL] "enet1_rgmii_tx_ctl",
+	[ENET1_RX_ER] "enet1_rx_er",
+	[ENET1_TX_CLK] "enet1_tx_clk",
+	[ENET1_TX_ER] "enet1_tx_er",
+	[GPIO1_IO00] "gpio1_io00",
+	[GPIO1_IO01] "gpio1_io01",
+	[GPIO1_IO02] "gpio1_io02",
+	[GPIO1_IO03] "gpio1_io03",
+	[GPIO1_IO04] "gpio1_io04",
+	[GPIO1_IO05] "gpio1_io05",
+	[GPIO1_IO06] "gpio1_io06",
+	[GPIO1_IO07] "gpio1_io07",
+	[GPIO1_IO08] "gpio1_io08",
+	[GPIO1_IO09] "gpio1_io09",
+	[GPIO1_IO10] "gpio1_io10",
+	[GPIO1_IO11] "gpio1_io11",
+	[GPIO1_IO12] "gpio1_io12",
+	[GPIO1_IO13] "gpio1_io13",
+	[GPIO1_IO14] "gpio1_io14",
+	[GPIO1_IO15] "gpio1_io15",
+	[GPIO1_IO16] "gpio1_io16",
+	[GPIO1_IO17] "gpio1_io17",
+	[GPIO1_IO18] "gpio1_io18",
+	[GPIO1_IO19] "gpio1_io19",
+	[GPIO1_IO20] "gpio1_io20",
+	[GPIO1_IO21] "gpio1_io21",
+	[GPIO1_IO22] "gpio1_io22",
+	[GPIO1_IO23] "gpio1_io23",
+	[GPIO1_IO24] "gpio1_io24",
+	[GPIO1_IO25] "gpio1_io25",
+	[GPIO1_IO26] "gpio1_io26",
+	[GPIO1_IO27] "gpio1_io27",
+	[GPIO1_IO28] "gpio1_io28",
+	[GPIO1_IO29] "gpio1_io29",
+	[GPIO2_IO00] "gpio2_io00",
+	[GPIO2_IO01] "gpio2_io01",
+	[GPIO2_IO02] "gpio2_io02",
+	[GPIO2_IO03] "gpio2_io03",
+	[GPIO2_IO04] "gpio2_io04",
+	[GPIO2_IO05] "gpio2_io05",
+	[GPIO2_IO06] "gpio2_io06",
+	[GPIO2_IO07] "gpio2_io07",
+	[GPIO2_IO08] "gpio2_io08",
+	[GPIO2_IO09] "gpio2_io09",
+	[GPIO2_IO10] "gpio2_io10",
+	[GPIO2_IO11] "gpio2_io11",
+	[GPIO2_IO12] "gpio2_io12",
+	[GPIO2_IO13] "gpio2_io13",
+	[GPIO2_IO14] "gpio2_io14",
+	[GPIO2_IO15] "gpio2_io15",
+	[GPIO2_IO16] "gpio2_io16",
+	[GPIO2_IO17] "gpio2_io17",
+	[GPIO2_IO18] "gpio2_io18",
+	[GPIO2_IO19] "gpio2_io19",
+	[GPIO2_IO20] "gpio2_io20",
+	[GPIO3_IO00] "gpio3_io00",
+	[GPIO3_IO01] "gpio3_io01",
+	[GPIO3_IO02] "gpio3_io02",
+	[GPIO3_IO03] "gpio3_io03",
+	[GPIO3_IO04] "gpio3_io04",
+	[GPIO3_IO05] "gpio3_io05",
+	[GPIO3_IO06] "gpio3_io06",
+	[GPIO3_IO07] "gpio3_io07",
+	[GPIO3_IO08] "gpio3_io08",
+	[GPIO3_IO09] "gpio3_io09",
+	[GPIO3_IO10] "gpio3_io10",
+	[GPIO3_IO11] "gpio3_io11",
+	[GPIO3_IO12] "gpio3_io12",
+	[GPIO3_IO13] "gpio3_io13",
+	[GPIO3_IO14] "gpio3_io14",
+	[GPIO3_IO15] "gpio3_io15",
+	[GPIO3_IO16] "gpio3_io16",
+	[GPIO3_IO17] "gpio3_io17",
+	[GPIO3_IO18] "gpio3_io18",
+	[GPIO3_IO19] "gpio3_io19",
+	[GPIO3_IO20] "gpio3_io20",
+	[GPIO3_IO21] "gpio3_io21",
+	[GPIO3_IO22] "gpio3_io22",
+	[GPIO3_IO23] "gpio3_io23",
+	[GPIO3_IO24] "gpio3_io24",
+	[GPIO3_IO25] "gpio3_io25",
+	[GPIO4_IO00] "gpio4_io00",
+	[GPIO4_IO01] "gpio4_io01",
+	[GPIO4_IO02] "gpio4_io02",
+	[GPIO4_IO03] "gpio4_io03",
+	[GPIO4_IO04] "gpio4_io04",
+	[GPIO4_IO05] "gpio4_io05",
+	[GPIO4_IO06] "gpio4_io06",
+	[GPIO4_IO07] "gpio4_io07",
+	[GPIO4_IO08] "gpio4_io08",
+	[GPIO4_IO09] "gpio4_io09",
+	[GPIO4_IO10] "gpio4_io10",
+	[GPIO4_IO11] "gpio4_io11",
+	[GPIO4_IO12] "gpio4_io12",
+	[GPIO4_IO13] "gpio4_io13",
+	[GPIO4_IO14] "gpio4_io14",
+	[GPIO4_IO15] "gpio4_io15",
+	[GPIO4_IO16] "gpio4_io16",
+	[GPIO4_IO17] "gpio4_io17",
+	[GPIO4_IO18] "gpio4_io18",
+	[GPIO4_IO19] "gpio4_io19",
+	[GPIO4_IO20] "gpio4_io20",
+	[GPIO4_IO21] "gpio4_io21",
+	[GPIO4_IO22] "gpio4_io22",
+	[GPIO4_IO23] "gpio4_io23",
+	[GPIO4_IO24] "gpio4_io24",
+	[GPIO4_IO25] "gpio4_io25",
+	[GPIO4_IO26] "gpio4_io26",
+	[GPIO4_IO27] "gpio4_io27",
+	[GPIO4_IO28] "gpio4_io28",
+	[GPIO4_IO29] "gpio4_io29",
+	[GPIO4_IO31] "gpio4_io31",
+	[GPIO5_IO00] "gpio5_io00",
+	[GPIO5_IO01] "gpio5_io01",
+	[GPIO5_IO02] "gpio5_io02",
+	[GPIO5_IO03] "gpio5_io03",
+	[GPIO5_IO04] "gpio5_io04",
+	[GPIO5_IO05] "gpio5_io05",
+	[GPIO5_IO06] "gpio5_io06",
+	[GPIO5_IO07] "gpio5_io07",
+	[GPIO5_IO08] "gpio5_io08",
+	[GPIO5_IO09] "gpio5_io09",
+	[GPIO5_IO10] "gpio5_io10",
+	[GPIO5_IO11] "gpio5_io11",
+	[GPIO5_IO12] "gpio5_io12",
+	[GPIO5_IO13] "gpio5_io13",
+	[GPIO5_IO14] "gpio5_io14",
+	[GPIO5_IO15] "gpio5_io15",
+	[GPIO5_IO16] "gpio5_io16",
+	[GPIO5_IO17] "gpio5_io17",
+	[GPIO5_IO18] "gpio5_io18",
+	[GPIO5_IO19] "gpio5_io19",
+	[GPIO5_IO20] "gpio5_io20",
+	[GPIO5_IO21] "gpio5_io21",
+	[GPIO5_IO22] "gpio5_io22",
+	[GPIO5_IO23] "gpio5_io23",
+	[GPIO5_IO24] "gpio5_io24",
+	[GPIO5_IO25] "gpio5_io25",
+	[GPIO5_IO26] "gpio5_io26",
+	[GPIO5_IO27] "gpio5_io27",
+	[GPIO5_IO28] "gpio5_io28",
+	[GPIO5_IO29] "gpio5_io29",
+	[GPT1_CAPTURE1] "gpt1_capture1",
+	[GPT1_CAPTURE2] "gpt1_capture2",
+	[GPT1_COMPARE1] "gpt1_compare1",
+	[GPT1_COMPARE2] "gpt1_compare2",
+	[GPT1_COMPARE3] "gpt1_compare3",
+	[GPT1_CLK] "gpt1_clk",
+	[GPT2_CLK] "gpt2_clk",
+	[GPT3_CLK] "gpt3_clk",
+	[I2C1_SCL] "i2c1_scl",
+	[I2C1_SDA] "i2c1_sda",
+	[I2C2_SCL] "i2c2_scl",
+	[I2C2_SDA] "i2c2_sda",
+	[I2C3_SCL] "i2c3_scl",
+	[I2C3_SDA] "i2c3_sda",
+	[I2C4_SCL] "i2c4_scl",
+	[I2C4_SDA] "i2c4_sda",
+	[M4_NMI] "m4_nmi",
+	[PCIE_CLKREQ_B] "pcie_clkreq_b",
+	[PWM1_OUT] "pwm1_out",
+	[PWM2_OUT] "pwm2_out",
+	[PWM3_OUT] "pwm3_out",
+	[PWM4_OUT] "pwm4_out",
+	[QSPI_A_DATA0] "qspi_a_data0",
+	[QSPI_A_DATA1] "qspi_a_data1",
+	[QSPI_A_DATA2] "qspi_a_data2",
+	[QSPI_A_DATA3] "qspi_a_data3",
+	[QSPI_A_DQS] "qspi_a_dqs",
+	[QSPI_A_SCLK] "qspi_a_sclk",
+	[QSPI_A_SS0_B] "qspi_a_ss0_b",
+	[QSPI_A_SS1_B] "qspi_a_ss1_b",
+	[QSPI_B_DATA0] "qspi_b_data0",
+	[QSPI_B_DATA1] "qspi_b_data1",
+	[QSPI_B_DATA2] "qspi_b_data2",
+	[QSPI_B_DATA3] "qspi_b_data3",
+	[QSPI_B_DQS] "qspi_b_dqs",
+	[QSPI_B_SCLK] "qspi_b_sclk",
+	[QSPI_B_SS0_B] "qspi_b_ss0_b",
+	[QSPI_B_SS1_B] "qspi_b_ss1_b",
+	[RAWNAND_ALE] "rawnand_ale",
+	[RAWNAND_CE0_B] "rawnand_ce0_b",
+	[RAWNAND_CE1_B] "rawnand_ce1_b",
+	[RAWNAND_CE2_B] "rawnand_ce2_b",
+	[RAWNAND_CE3_B] "rawnand_ce3_b",
+	[RAWNAND_CLE] "rawnand_cle",
+	[RAWNAND_DATA00] "rawnand_data00",
+	[RAWNAND_DATA01] "rawnand_data01",
+	[RAWNAND_DATA02] "rawnand_data02",
+	[RAWNAND_DATA03] "rawnand_data03",
+	[RANWNAD_DATA04] "ranwnad_data04",
+	[RAWNAND_DATA05] "rawnand_data05",
+	[RAWNAND_DATA06] "rawnand_data06",
+	[RAWNAND_DATA07] "rawnand_data07",
+	[RAWNAND_DQS] "rawnand_dqs",
+	[RAWNAND_READY_B] "rawnand_ready_b",
+	[RAWNAND_RE_B] "rawnand_re_b",
+	[RAWNAND_WE_B] "rawnand_we_b",
+	[RAWNAND_WP_B] "rawnand_wp_b",
+	[SAI1_MCLK] "sai1_mclk",
+	[SAI1_RX_DATA0] "sai1_rx_data0",
+	[SAI1_RX_DATA1] "sai1_rx_data1",
+	[SAI1_RX_DATA2] "sai1_rx_data2",
+	[SAI1_RX_DATA3] "sai1_rx_data3",
+	[SAI1_RX_DATA4] "sai1_rx_data4",
+	[SAI1_RX_DATA5] "sai1_rx_data5",
+	[SAI1_RX_DATA6] "sai1_rx_data6",
+	[SAI1_RX_DATA7] "sai1_rx_data7",
+	[SAI1_TX_BCLK] "sai1_tx_bclk",
+	[SAI1_TX_DATA0] "sai1_tx_data0",
+	[SAI1_TX_DATA1] "sai1_tx_data1",
+	[SAI1_TX_DATA2] "sai1_tx_data2",
+	[SAI1_TX_DATA3] "sai1_tx_data3",
+	[SAI1_TX_DATA4] "sai1_tx_data4",
+	[SAI1_TX_DATA5] "sai1_tx_data5",
+	[SAI1_TX_DATA6] "sai1_tx_data6",
+	[SAI1_TX_DATA7] "sai1_tx_data7",
+	[SAI2_MCLK] "sai2_mclk",
+	[SAI2_RX_BCLK] "sai2_rx_bclk",
+	[SAI2_RX_DATA0] "sai2_rx_data0",
+	[SAI2_RX_SYNC] "sai2_rx_sync",
+	[SAI2_TX_BCLK] "sai2_tx_bclk",
+	[SAI2_TX_DATA0] "sai2_tx_data0",
+	[SAI2_TX_SYNC] "sai2_tx_sync",
+	[SAI3_MCLK] "sai3_mclk",
+	[SAI3_RX_BCLK] "sai3_rx_bclk",
+	[SAI3_RX_DATA0] "sai3_rx_data0",
+	[SAI3_RX_SYNC] "sai3_rx_sync",
+	[SAI3_TX_BCLK] "sai3_tx_bclk",
+	[SAI3_TX_DATA0] "sai3_tx_data0",
+	[SAI3_TX_SYNC] "sai3_tx_sync",
+	[SAI4_MCLK] "sai4_mclk",
+	[SAI5_RX_DATA0] "sai5_rx_data0",
+	[SAI5_RX_DATA1] "sai5_rx_data1",
+	[SAI5_RX_DATA2] "sai5_rx_data2",
+	[SAI5_RX_DATA3] "sai5_rx_data3",
+	[SAI5_TX_BCLK] "sai5_tx_bclk",
+	[SAI5_TX_DATA0] "sai5_tx_data0",
+	[SAI5_TX_DATA1] "sai5_tx_data1",
+	[SAI5_TX_DATA2] "sai5_tx_data2",
+	[SAI5_TX_DATA3] "sai5_tx_data3",
+	[SAI6_RC_BCLK] "sai6_rc_bclk",
+	[SAI6_RX_DATA0] "sai6_rx_data0",
+	[SAI6_TX_DATA0] "sai6_tx_data0",
+	[SAI6_TX_SYNC] "sai6_tx_sync",
+	[SDMA1_EXT_EVENT0] "sdma1_ext_event0",
+	[SDMA1_EXT_EVENT1] "sdma1_ext_event1",
+	[SDMA2_EXT_EVENT0] "sdma2_ext_event0",
+	[SDMA2_EXT_EVENT1] "sdma2_ext_event1",
+	[SJC_DE_B] "sjc_de_b",
+	[SPDIF1_EXT_CLK] "spdif1_ext_clk",
+	[SPDIF1_IN] "spdif1_in",
+	[SPDIF1_OUT] "spdif1_out",
+	[SRC_BOOT_CFG0] "src_boot_cfg0",
+	[SRC_BOOT_CFG1] "src_boot_cfg1",
+	[SRC_BOOT_CFG2] "src_boot_cfg2",
+	[SRC_BOOT_CFG3] "src_boot_cfg3",
+	[SRC_BOOT_CFG4] "src_boot_cfg4",
+	[SRC_BOOT_CFG5] "src_boot_cfg5",
+	[SRC_BOOT_CFG6] "src_boot_cfg6",
+	[SRC_BOOT_CFG7] "src_boot_cfg7",
+	[SRC_BOOT_CFG8] "src_boot_cfg8",
+	[SRC_BOOT_CFG9] "src_boot_cfg9",
+	[SRC_BOOT_CFG10] "src_boot_cfg10",
+	[SRC_BOOT_CFG11] "src_boot_cfg11",
+	[SRC_BOOT_CFG12] "src_boot_cfg12",
+	[SRC_BOOT_CFG13] "src_boot_cfg13",
+	[SRC_BOOT_CFG14] "src_boot_cfg14",
+	[SRC_BOOT_CFG15] "src_boot_cfg15",
+	[UART1_CTS_B] "uart1_cts_b",
+	[UART1_RX] "uart1_rx",
+	[UART1_TX] "uart1_tx",
+	[UART2_CTS_B] "uart2_cts_b",
+	[UART2_RX] "uart2_rx",
+	[UART2_TX] "uart2_tx",
+	[UART3_CTS_B] "uart3_cts_b",
+	[UART3_RX] "uart3_rx",
+	[UART3_TX] "uart3_tx",
+	[UART4_CTS_B] "uart4_cts_b",
+	[UART4_RX] "uart4_rx",
+	[UART4_TX] "uart4_tx",
+	[USB1_OTG_ID] "usb1_otg_id",
+	[USB1_OTG_OC] "usb1_otg_oc",
+	[USB1_OTG_PWR] "usb1_otg_pwr",
+	[USB2_OTG_ID] "usb2_otg_id",
+	[USB2_OTG_OC] "usb2_otg_oc",
+	[USB2_OTG_PWR] "usb2_otg_pwr",
+	[USDHC1_CD_B] "usdhc1_cd_b",
+	[USDHC1_CLK] "usdhc1_clk",
+	[USDHC1_CMD] "usdhc1_cmd",
+	[USDHC1_DATA0] "usdhc1_data0",
+	[USDHC1_DATA1] "usdhc1_data1",
+	[USDHC1_DATA2] "usdhc1_data2",
+	[USDHC1_DATA3] "usdhc1_data3",
+	[USDHC1_DATA4] "usdhc1_data4",
+	[USDHC1_DATA5] "usdhc1_data5",
+	[USDHC1_DATA6] "usdhc1_data6",
+	[USDHC1_DATA7] "usdhc1_data7",
+	[USDHC1_RESET_B] "usdhc1_reset_b",
+	[USDHC1_STROBE] "usdhc1_strobe",
+	[USDHC1_VSELECT] "usdhc1_vselect",
+	[USDHC1_WP] "usdhc1_wp",
+	[USDHC2_CD_B] "usdhc2_cd_b",
+	[USDHC2_CLK] "usdhc2_clk",
+	[USDHC2_CMD] "usdhc2_cmd",
+	[USDHC2_DATA0] "usdhc2_data0",
+	[USDHC2_DATA1] "usdhc2_data1",
+	[USDHC2_DATA2] "usdhc2_data2",
+	[USDHC2_DATA3] "usdhc2_data3",
+	[USDHC2_RESET_B] "usdhc2_reset_b",
+	[USDHC2_VSELECT] "usdhc2_vselect",
+	[USDHC2_WP] "usdhc2_wp",
+	[WDOG1_WDOG_ANY] "wdog1_wdog_any",
+	[WDOG1_WDOG_B] "wdog1_wdog_b",
+};
+
+struct padopt {
+	char	*s;
+	u32int	m;
+	u32int	v;
+};
+
+static struct padopt padopts[] = {
+	"VSEL_0",	7<<11,	0<<11,
+	"VSEL_1",	7<<11,	1<<11,
+	"VSEL_2",	7<<11,	2<<11,
+	"VSEL_3",	7<<11,	3<<11,
+	"VSEL_4",	7<<11,	4<<11,
+	"VSEL_5",	7<<11,	5<<11,
+	"VSEL_6",	7<<11,	6<<11,
+	"VSEL_7",	7<<11,	7<<11,
+
+	"LVTTL_OFF",	1<<8,	0<<8,
+	"LVTTL",	1<<8,	1<<8,
+
+	"HYS_OFF",	1<<7,	0<<7,
+	"HYS",		1<<7,	1<<7,
+
+	"PUE",		1<<6,	1<<6,
+	"PUD",		1<<6,	0<<6,
+
+	"ODE",		1<<5,	1<<5,
+	"ODD",		1<<5,	0<<5,
+
+	"SLOW",		3<<3,	0<<3,
+	"MEDIUM",	3<<3,	1<<3,
+	"FAST",		3<<3,	2<<3,
+	"MAX",		3<<3,	3<<3,
+
+	/* DSE */
+	"HI-Z",		7,	0,
+	"255_OHM",	7,	1,
+	"105_OHM",	7,	2,
+	"75_OHM",	7,	3,
+	"85_OHM",	7,	4,
+	"65_OHM",	7,	5,
+	"45_OHM",	7,	6,
+	"40_OHM",	7,	7,
+
+	nil,
+};
+
+void
+iomuxpad(char *pads, char *sel, char *cfg)
+{
+	int pad, sig, mux, alt, daisy;
+	u32int val, mask, *reg;
+
+	for(pad = 0; pad < nelem(padname); pad++)
+		if(padname[pad] != nil && cistrcmp(pads, padname[pad]) == 0)
+			goto Padok;
+
+	panic("iomuxpad: %s not defined", pads);
+	return;
+Padok:
+	val = 0;
+	mask = 0;
+	mux = 0;
+	sig = 0;
+
+	if(cfg != nil){
+		struct padopt *o;
+
+		for(o = padopts; o->s != nil; o++) {
+			if(strstr(cfg, o->s) != nil){
+				val |= o->v;
+				mask |= o->m;
+			}
+		}
+		if(mask != 0){
+			reg = &iomuxc[IOMUXC_SW_PAD_CTL_PAD_TEST_MODE + pad];
+// iprint("iomuxpad: pad_ctl_%s %p <= %.8ux & %.8ux\n", padname[pad], PADDR(reg), val, mask);
+			*reg = (*reg & ~mask) | val;
+		}
+
+		val = 0;
+		mask = 0;
+		if(strstr(cfg, "SION") != nil){
+			val |= SION;
+			mask |= SION;
+		}
+		if(strstr(cfg, "SIOFF") != nil){
+			val &= ~SION;
+			mask |= SION;
+		}
+	}
+
+	if(sel != nil){
+		if(pad < PAD_GPIO1_IO00 || pad >= nelem(padmux)/8)
+			panic("iomuxpad: %s is not muxed", pads);
+
+		/* find the mux value for the signal */
+		for(alt = 0; alt < 8; alt++){
+			mux = padmux[pad*8 + alt];
+			if(mux == 0)
+				continue;
+
+			sig = mux & ~DAISY(7);
+			if(signame[sig] != nil && cistrcmp(sel, signame[sig]) == 0)
+				goto Muxok;
+		}
+		panic("iomuxpad: %s not muxable to %s", pads, sel);
+		return;
+Muxok:
+		val = (val & ~MUX_MODE) | alt;
+		mask |= MUX_MODE;
+	}
+
+	if(mask == 0)
+		return;
+
+	if(pad < PAD_PMIC_STBY_REQ){
+		panic("iomuxpad: %s has no mux control", pads);
+		return;
+	}
+
+	reg = &iomuxc[IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ + (pad - PAD_PMIC_STBY_REQ)];
+// iprint("iomuxpad: mux_ctl_%s %p <= %.8ux & %.8ux (%s)\n", padname[pad], PADDR(reg), val, mask, signame[sig]);
+	*reg = (*reg & ~mask) | val;
+
+	if((mux & DAISY(0)) == 0)
+		return;
+
+	val = DAISY_VAL(mux);
+
+	/* configure daisy input mux */
+	assert(sig < nelem(daisytab));
+	daisy = daisytab[sig];
+	assert(daisy != 0);
+	mask = DAISY_VAL(daisy);
+	assert((mask & (mask+1)) == 0);
+	daisy &= ~DAISY(7);
+
+	reg = &iomuxc[IOMUXC_CCM_PMIC_READY_SELECT_INPUT + daisy];
+// iprint("iomuxpad: %s_input_select %p <= %.8ux & %.8ux\n", signame[sig], PADDR(reg), val, mask);
+	*reg = (*reg & ~mask) | val;
+}
diff --git a/sys/src/9/imx8/lcd.c b/sys/src/9/imx8/lcd.c
index 15a10d544..686ee9aa8 100644
--- a/sys/src/9/imx8/lcd.c
+++ b/sys/src/9/imx8/lcd.c
@@ -16,12 +16,6 @@ extern Memimage *gscreen;
 
 /* pinmux registers */
 enum {
-	IOMUXC_CTL_PAD_SAI5_RXC = 0x144/4,	/* for gpio3 20 */
-	IOMUXC_CTL_PAD_SPDIF_RX = 0x1EC/4,	/* for pwm2 */
-	IOMUXC_CTL_PAD_GPIO1_IO10 = 0x50/4,	/* for gpio1 10 */
-		SION = 1<<4,
-		MUX_MODE = 7,
-
 	IOMUXC_GPR_GPR13	= 0x10034/4,	/* GPR13 for MIPI_MUX_SEL */
 		MIPI_MUX_SEL = 1<<2,
 		MIPI_MUX_INV = 1<<3,
@@ -825,13 +819,15 @@ lcdinit(void)
 	I2Cdev *bridge;
 	char *err;
 
-	/* gpio3 20 for sn65dsi86 bridge */
-	mr(iomuxc, IOMUXC_CTL_PAD_SAI5_RXC, 5, MUX_MODE);
-	/* gpio1 10 pad for panel */
-	mr(iomuxc, IOMUXC_CTL_PAD_GPIO1_IO10, 0, MUX_MODE);
-	/* pwm2 pad */
-	mr(iomuxc, IOMUXC_CTL_PAD_SPDIF_RX, 1, MUX_MODE);
+	/* gpio3_io20: sn65dsi86 bridge */
+	iomuxpad("pad_sai5_rxc", "gpio3_io20", nil);
 
+	/* gpio1_io10: for panel */
+	iomuxpad("pad_gpio1_io10", "gpio1_io10", nil);	
+
+	/* pwm2_out: for panel backlight */
+	iomuxpad("pad_spdif_rx", "pwm2_out", nil);
+	
 	/* lcdif to dpi=0, dcss=1 */
 	mr(iomuxc, IOMUXC_GPR_GPR13, 0, MIPI_MUX_SEL);
 
diff --git a/sys/src/9/imx8/reform b/sys/src/9/imx8/reform
index ff00d402c..65191bfa9 100644
--- a/sys/src/9/imx8/reform
+++ b/sys/src/9/imx8/reform
@@ -40,6 +40,7 @@ misc
 	gic
 	uartimx
 	lcd
+	iomux
 port
 	int cpuserver = 0;
 bootdir
diff --git a/sys/src/9/imx8/usbxhciimx.c b/sys/src/9/imx8/usbxhciimx.c
index ea08d002e..1dd2f6537 100644
--- a/sys/src/9/imx8/usbxhciimx.c
+++ b/sys/src/9/imx8/usbxhciimx.c
@@ -1875,16 +1875,8 @@ reset(Hci *hp)
 
 Found:
 	if(i == 0){
-		static u32int *iomuxc = (u32int*)(VIRTIO + 0x330000);
-		enum {
-			IOMUXC_CTL_PAD_GPIO1_IO13 = 0x5C/4,	/* for gpio1 13 */
-			IOMUXC_CTL_PAD_GPIO1_IO14 = 0x60/4,	/* for gpio1 14 */
-
-			IOMUXC_SW_PAD_CTRL_PAD_GPIO1_IO14 = 0x2C8/4,
-		};
-		iomuxc[IOMUXC_CTL_PAD_GPIO1_IO13] = 1;
-		iomuxc[IOMUXC_CTL_PAD_GPIO1_IO14] = 0;
-		iomuxc[IOMUXC_SW_PAD_CTRL_PAD_GPIO1_IO14] = 0x16;
+		iomuxpad("pad_gpio1_io13", "usb1_otg_oc", nil);
+		iomuxpad("pad_gpio1_io14", "gpio1_io14", "FAST 45_OHM");
 
 		hubreset(0);
 		microdelay(500);