igfx: fix sandybridge fdi link training bits and ordering
- fix wrong bitfield for txctl (different between snb and ivb), and enable tx before rx - DPLL_CTL_x snb/ivb: don't touch reserved bits
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faae8eb752
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8c358c3f97
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@ -869,7 +869,8 @@ initdpll(Igfx *igfx, int x, int freq, int port)
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dpll->ctrl.v &= ~(1<<30);
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dpll->ctrl.v &= ~(1<<30);
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/* VGA Mode Disable */
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/* VGA Mode Disable */
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dpll->ctrl.v |= (1<<28);
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if(igfx->type == TypeG45)
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dpll->ctrl.v |= (1<<28);
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dpll->fp0.v &= ~(0x3f<<16);
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dpll->fp0.v &= ~(0x3f<<16);
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dpll->fp0.v |= n << 16;
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dpll->fp0.v |= n << 16;
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@ -1394,7 +1395,11 @@ enablepipe(Igfx *igfx, int x)
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p->fdi->rxctl.v |= (1<<4); /* pcdclk */
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p->fdi->rxctl.v |= (1<<4); /* pcdclk */
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loadreg(igfx, p->fdi->rxctl);
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loadreg(igfx, p->fdi->rxctl);
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sleep(5);
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sleep(5);
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p->fdi->txctl.v &= ~(7<<8 | 1); /* clear auto training bits */
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/* clear auto training bits */
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if(igfx->type == TypeSNB)
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p->fdi->txctl.v &= ~(3<<28 | 1<<10 | 1);
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else
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p->fdi->txctl.v &= ~(7<<8 | 1);
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p->fdi->txctl.v &= ~(1<<31); /* disable */
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p->fdi->txctl.v &= ~(1<<31); /* disable */
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p->fdi->txctl.v |= (1<<14); /* enable pll */
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p->fdi->txctl.v |= (1<<14); /* enable pll */
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loadreg(igfx, p->fdi->txctl);
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loadreg(igfx, p->fdi->txctl);
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@ -1449,14 +1454,14 @@ enablepipe(Igfx *igfx, int x)
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/* unmask bit lock and symbol lock bits */
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/* unmask bit lock and symbol lock bits */
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csr(igfx, p->fdi->rximr.a, 3<<8, 0);
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csr(igfx, p->fdi->rximr.a, 3<<8, 0);
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p->fdi->txctl.v &= ~(3<<28); /* link train pattern1 */
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p->fdi->txctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->txctl);
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p->fdi->rxctl.v &= ~(3<<8); /* link train pattern1 */
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p->fdi->rxctl.v &= ~(3<<8); /* link train pattern1 */
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p->fdi->rxctl.v |= 1<<31; /* enable */
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p->fdi->rxctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->rxctl);
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loadreg(igfx, p->fdi->rxctl);
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p->fdi->txctl.v &= ~(3<<8); /* link train pattern1 */
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p->fdi->txctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->txctl);
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/* wait for bit lock */
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/* wait for bit lock */
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for(i=0; i<10; i++){
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for(i=0; i<10; i++){
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sleep(1);
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sleep(1);
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@ -1466,8 +1471,8 @@ enablepipe(Igfx *igfx, int x)
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csr(igfx, p->fdi->rxiir.a, 0, 1<<8);
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csr(igfx, p->fdi->rxiir.a, 0, 1<<8);
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/* switch to link train pattern2 */
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/* switch to link train pattern2 */
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csr(igfx, p->fdi->txctl.a, 3<<28, 1<<28);
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csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
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csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
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csr(igfx, p->fdi->txctl.a, 3<<8, 1<<8);
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/* wait for symbol lock */
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/* wait for symbol lock */
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for(i=0; i<10; i++){
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for(i=0; i<10; i++){
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@ -1478,8 +1483,8 @@ enablepipe(Igfx *igfx, int x)
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csr(igfx, p->fdi->rxiir.a, 0, 1<<9);
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csr(igfx, p->fdi->rxiir.a, 0, 1<<9);
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/* switch to link train normal */
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/* switch to link train normal */
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csr(igfx, p->fdi->txctl.a, 0, 3<<28);
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csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
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csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
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csr(igfx, p->fdi->txctl.a, 0, 3<<8);
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/* wait idle pattern time */
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/* wait idle pattern time */
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sleep(5);
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sleep(5);
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