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remove old copies of kernels l.s from cmd/?a

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This commit is contained in:
cinap_lenrek 2014-05-08 18:48:51 +02:00
parent 47d131c088
commit 87fd5240f0
7 changed files with 0 additions and 3130 deletions
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479
sys/src/cmd/1a/l.s
View file

@ -1,479 +0,0 @@
/*
* Memory and machine-specific definitions. Used in C and assembler.
*/
/*
* Sizes
*/
#define BI2BY 8 /* bits per byte */
#define BI2WD 32 /* bits per word */
#define BY2WD 4 /* bytes per word */
#define BY2PG 8192 /* bytes per page */
#define WD2PG (BY2PG/BY2WD) /* words per page */
#define PGSHIFT 13 /* log(BY2PG) */
#define PGROUND(s) (((s)+(BY2PG-1))&~(BY2PG-1))
#define ICACHESIZE 0
#define MB4 (4*1024*1024) /* Lots of things are 4Mb in size */
#define MAXMACH 1 /* max # cpus system can run */
/*
* Time
*/
#define HZ (60) /* clock frequency */
#define MS2HZ (1000/HZ) /* millisec per clock tick */
#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
#define TK2MS(t) ((((ulong)(t))*1000)/HZ) /* ticks to milliseconds */
#define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */
/*
* SR bits
*/
#define SUPER 0x2000
#define SPL(n) (n<<8)
/*
* CACR
*/
#define CCLEAR 0x08
#define CENABLE 0x01
/*
* Magic registers (unused in current system)
*/
#define MACH A5 /* A5 is m-> */
#define USER A4 /* A4 is u-> */
/*
* Fundamental addresses
*/
#define USERADDR 0x80000000
/* assuming we're in a syscall, this is the address of the Ureg structure */
#define UREGVARSZ (23*BY2WD) /* size of variable part of Ureg */
#define UREGADDR (USERADDR+BY2PG-(UREGVARSZ+2+4+2+(8+8+1+1)*BY2WD))
/*
* Devices poked during bootstrap
*/
#define TACADDR 0x40600000
#define MOUSE 0x40200000
/*
* MMU
*/
#define VAMASK 0xCFFFFFFF /* clear balu bits in address */
#define KUSEG 0x00000000
#define KSEG 0x80000000
/*
* MMU entries
*/
#define PTEVALID (1<<13)
#define PTEWRITE 0
#define PTERONLY (1<<14)
#define PTEKERNEL (1<<15)
#define PTEUNCACHED 0
#define INVALIDPTE 0
#define PTEMAPMEM (1024*1024)
#define PTEPERTAB (PTEMAPMEM/BY2PG)
#define SEGMAPSIZE 16
#define PPN(pa) ((pa>>13)&0x1FFF)
#define KMAP ((unsigned long *)0xD0000000)
#define UMAP ((unsigned long *)0x50000000)
/*
* Virtual addresses
*/
#define VTAG(va) ((va>>22)&0x03F)
#define VPN(va) ((va>>13)&0x1FF)
#define PARAM ((char*)0x40500000)
#define TLBFLUSH_ 0x01
/*
* Address spaces
*/
#define UZERO KUSEG /* base of user address space */
#define UTZERO (UZERO+BY2PG) /* first address in user text */
#define TSTKTOP 0x10000000 /* end of new stack in sysexec */
#define TSTKSIZ 100
#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
#define KZERO KSEG /* base of kernel address space */
#define KTZERO (KZERO+BY2PG) /* first address in kernel text */
#define USTKSIZE (4*1024*1024) /* size of user stack */
#define MACHSIZE 4096
#define isphys(p) ((((ulong)(p))&0xF0000000) == KSEG)
#define DBMAGIC 0xBADC0C0A
/*
* Boot first processor
*/
TEXT start(SB), $-4
MOVW $(SUPER|SPL(7)), SR
MOVL $a6base(SB), A6
MOVL $0, R0
MOVL R0, CACR
MOVL R0, TACADDR /* zero tac counter (cause an intr?) */
MOVL $mach0(SB), A0
MOVL A0, m(SB)
MOVL $0, 0(A0)
MOVL A0, A7
ADDL $(MACHSIZE-4), A7 /* start stack under machine struct */
MOVL $0, u(SB)
MOVL $vectors(SB), A0
MOVL A0, VBR
BSR main(SB)
/* never returns */
dead:
BRA dead
/*
* Take first processor into user mode. Leave enough room on the stack
* for a full-sized Ureg (including long bus error format) to fit
*/
TEXT touser(SB), $-4
MOVL $(USERADDR+BY2PG-UREGVARSZ), A7
MOVW $0, -(A7)
MOVL $(UTZERO+32), -(A7) /* header is in text */
MOVW $0, -(A7)
MOVL $(USTKTOP-6*BY2WD), A0 /* MAXSYSARG=6 */
MOVL A0, USP
MOVW $(SUPER|SPL(0)), SR
MOVL $8, R0
MOVL R0, CACR
RTE
TEXT firmware(SB), $0
MOVL $0x40000090, A0
JMP (A0)
TEXT splhi(SB), $0
MOVL m(SB), A0
MOVL (A7), 4(A0)
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(7)), SR
RTS
TEXT splduart(SB), $0
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(5)), SR
RTS
TEXT spllo(SB), $0
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(0)), SR
RTS
TEXT splx(SB), $0
MOVL sr+0(FP), R0
MOVW R0, SR
RTS
TEXT spldone(SB), $0
RTS
TEXT spl1(SB), $0
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(1)), SR
RTS
TEXT flushcpucache(SB), $0
MOVL $(CCLEAR|CENABLE), R0
MOVL R0, CACR
RTS
TEXT cacrtrap(SB), $0 /* user entry point to control cache, e.g. flush */
MOVL R0, CACR
RTE
TEXT setlabel(SB), $0
MOVL sr+0(FP), A0
MOVL A7, (A0)+ /* stack pointer */
MOVL (A7), (A0)+ /* pc of caller */
MOVW SR, (A0)+ /* status register */
CLRL R0 /* ret 0 => not returning */
RTS
TEXT gotolabel(SB), $0
MOVL p+0(FP), A0
MOVW $(SUPER|SPL(7)), SR
MOVL (A0)+, A7 /* stack pointer */
MOVL (A0)+, (A7) /* pc; stuff into stack frame */
MOVW (A0)+, R0 /* status register */
MOVW R0, SR
MOVL $1, R0 /* ret 1 => returning */
RTS
/*
* Test and set, as a subroutine
*/
TEXT tas(SB), $0
MOVL $0, R0
MOVL a+0(FP), A0
TAS (A0)
BEQ tas_1
MOVL $1, R0
tas_1:
RTS
/*
* Floating point
*/
TEXT fpsave(SB), $0
FSAVE (fp+0(FP))
RTS
TEXT fprestore(SB), $0
FRESTORE (fp+0(FP))
RTS
TEXT fpregsave(SB), $0
FMOVEM $0xFF, (3*4)(fr+0(FP))
FMOVEMC $0x7, (fr+0(FP))
RTS
TEXT fpregrestore(SB), $0
FMOVEMC (fr+0(FP)), $0x7
FMOVEM (3*4)(fr+0(FP)), $0xFF
RTS
TEXT fpcr(SB), $0
MOVL new+0(FP), R1
MOVL FPCR, R0
MOVL R1, FPCR
RTS
TEXT rfnote(SB), $0
MOVL uregp+0(FP), A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1+1)*BY2WD), A7
RTE
TEXT illegal(SB), $0
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR trap(SB)
ADDL $4, A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1)*BY2WD+BY2WD), A7
RTE
TEXT systrap(SB), $0
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVL A6, ((8+6)*BY2WD)(A7)
MOVL R0, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR syscall(SB)
MOVL ((1+8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVL ((1+8+6)*BY2WD)(A7), A6
ADDL $((1+8+8+1)*BY2WD+BY2WD), A7
RTE
TEXT buserror(SB), $0
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
PEA ((8+8+1+3)*BY2WD)(A7)
PEA 4(A7)
BSR fault68020(SB)
ADDL $8, A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1)*BY2WD+BY2WD), A7
RTE
TEXT tacintr(SB), $0 /* level 1 */
MOVL R0, -(A7)
MOVL TACADDR, R0
MOVL (A7)+, R0
RTE
TEXT portintr(SB), $0 /* level 2 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR devportintr(SB)
BRA retintr
TEXT dkintr(SB), $0 /* level 3 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR inconintr(SB)
BRA retintr
TEXT mouseintr(SB), $0 /* level 4 */
MOVEM $0x80C2, -(A7) /* D0, A0, A1, A6 */
MOVL $a6base(SB), A6
MOVL $15, R0 /* mask off hex switch */
ANDB MOUSE,R0 /* clears quadrature interrupt */
LEA mousetab(SB)(R0.W*8), A0
LEA mouse(SB), A1
MOVL (A0)+, R0
ADDL R0, (A1)+ /* dx */
MOVL (A0), R0
ADDL R0, (A1)+ /* dy */
ADDL $1, (A1) /* track */
MOVEM (A7)+, $0x4301
RTE
TEXT uartintr(SB), $0 /* level 5 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR duartintr(SB)
BRA retintr
TEXT syncintr(SB), $0 /* level 6 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR clock(SB)
/* fall through */
retintr:
BSR mousetry(SB)
ADDL $4, A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1)*BY2WD+BY2WD), A7
RTE
GLOBL duarttimer+0(SB),$4
TEXT duartreadtimer+0(SB), $0
MOVW SR, R1 /* spl7() */
MOVW $0x2700, SR
MOVL $0x40100000, A0
CLRL R0
TSTB 15(A0) /* stop timer */
MOVW 6(A0), R0 /* read hi,lo */
TSTB 14(A0) /* restart timer */
NOTW R0 /* timer counts down from 0xffff */
ADDL duarttimer(SB), R0
MOVL R0, duarttimer(SB)
MOVW R1, SR
RTS
GLOBL mousetab(SB), $128
DATA mousetab+ 0(SB)/4, -1 /* x down, */
DATA mousetab+ 4(SB)/4, 1 /* y up */
DATA mousetab+ 8(SB)/4, 0 /* x - */
DATA mousetab+ 12(SB)/4, 1 /* y up */
DATA mousetab+ 16(SB)/4, 1 /* x up */
DATA mousetab+ 20(SB)/4, 1 /* y up */
DATA mousetab+ 24(SB)/4, 0 /* x - */
DATA mousetab+ 28(SB)/4, 1 /* y up */
DATA mousetab+ 32(SB)/4, -1 /* x down */
DATA mousetab+ 36(SB)/4, 0 /* y - */
DATA mousetab+ 40(SB)/4, 0 /* x - */
DATA mousetab+ 44(SB)/4, 0 /* y - */
DATA mousetab+ 48(SB)/4, 1 /* x up, */
DATA mousetab+ 52(SB)/4, 0 /* y - */
DATA mousetab+ 56(SB)/4, 0 /* x - */
DATA mousetab+ 60(SB)/4, 0 /* y - */
DATA mousetab+ 64(SB)/4, -1 /* x down */
DATA mousetab+ 68(SB)/4, -1 /* y down */
DATA mousetab+ 72(SB)/4, 0 /* x - */
DATA mousetab+ 76(SB)/4, -1 /* y down */
DATA mousetab+ 80(SB)/4, 1 /* x up */
DATA mousetab+ 84(SB)/4, -1 /* y down */
DATA mousetab+ 88(SB)/4, 0 /* x - */
DATA mousetab+ 92(SB)/4, -1 /* y down */
DATA mousetab+ 96(SB)/4, -1 /* x down */
DATA mousetab+100(SB)/4, 0 /* y - */
DATA mousetab+104(SB)/4, 0 /* x - */
DATA mousetab+108(SB)/4, 0 /* y - */
DATA mousetab+112(SB)/4, 1 /* x up */
DATA mousetab+116(SB)/4, 0 /* y - */
DATA mousetab+120(SB)/4, 0 /* x - */
DATA mousetab+124(SB)/4, 0 /* y - */
GLOBL mach0+0(SB), $MACHSIZE
GLOBL u(SB), $4
GLOBL m(SB), $4

479
sys/src/cmd/2a/l.s
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@ -1,479 +0,0 @@
/*
* Memory and machine-specific definitions. Used in C and assembler.
*/
/*
* Sizes
*/
#define BI2BY 8 /* bits per byte */
#define BI2WD 32 /* bits per word */
#define BY2WD 4 /* bytes per word */
#define BY2PG 8192 /* bytes per page */
#define WD2PG (BY2PG/BY2WD) /* words per page */
#define PGSHIFT 13 /* log(BY2PG) */
#define PGROUND(s) (((s)+(BY2PG-1))&~(BY2PG-1))
#define ICACHESIZE 0
#define MB4 (4*1024*1024) /* Lots of things are 4Mb in size */
#define MAXMACH 1 /* max # cpus system can run */
/*
* Time
*/
#define HZ (60) /* clock frequency */
#define MS2HZ (1000/HZ) /* millisec per clock tick */
#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
#define TK2MS(t) ((((ulong)(t))*1000)/HZ) /* ticks to milliseconds */
#define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */
/*
* SR bits
*/
#define SUPER 0x2000
#define SPL(n) (n<<8)
/*
* CACR
*/
#define CCLEAR 0x08
#define CENABLE 0x01
/*
* Magic registers (unused in current system)
*/
#define MACH A5 /* A5 is m-> */
#define USER A4 /* A4 is u-> */
/*
* Fundamental addresses
*/
#define USERADDR 0x80000000
/* assuming we're in a syscall, this is the address of the Ureg structure */
#define UREGVARSZ (23*BY2WD) /* size of variable part of Ureg */
#define UREGADDR (USERADDR+BY2PG-(UREGVARSZ+2+4+2+(8+8+1+1)*BY2WD))
/*
* Devices poked during bootstrap
*/
#define TACADDR 0x40600000
#define MOUSE 0x40200000
/*
* MMU
*/
#define VAMASK 0xCFFFFFFF /* clear balu bits in address */
#define KUSEG 0x00000000
#define KSEG 0x80000000
/*
* MMU entries
*/
#define PTEVALID (1<<13)
#define PTEWRITE 0
#define PTERONLY (1<<14)
#define PTEKERNEL (1<<15)
#define PTEUNCACHED 0
#define INVALIDPTE 0
#define PTEMAPMEM (1024*1024)
#define PTEPERTAB (PTEMAPMEM/BY2PG)
#define SEGMAPSIZE 16
#define PPN(pa) ((pa>>13)&0x1FFF)
#define KMAP ((unsigned long *)0xD0000000)
#define UMAP ((unsigned long *)0x50000000)
/*
* Virtual addresses
*/
#define VTAG(va) ((va>>22)&0x03F)
#define VPN(va) ((va>>13)&0x1FF)
#define PARAM ((char*)0x40500000)
#define TLBFLUSH_ 0x01
/*
* Address spaces
*/
#define UZERO KUSEG /* base of user address space */
#define UTZERO (UZERO+BY2PG) /* first address in user text */
#define TSTKTOP 0x10000000 /* end of new stack in sysexec */
#define TSTKSIZ 100
#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
#define KZERO KSEG /* base of kernel address space */
#define KTZERO (KZERO+BY2PG) /* first address in kernel text */
#define USTKSIZE (4*1024*1024) /* size of user stack */
#define MACHSIZE 4096
#define isphys(p) ((((ulong)(p))&0xF0000000) == KSEG)
#define DBMAGIC 0xBADC0C0A
/*
* Boot first processor
*/
TEXT start(SB), $-4
MOVW $(SUPER|SPL(7)), SR
MOVL $a6base(SB), A6
MOVL $0, R0
MOVL R0, CACR
MOVL R0, TACADDR /* zero tac counter (cause an intr?) */
MOVL $mach0(SB), A0
MOVL A0, m(SB)
MOVL $0, 0(A0)
MOVL A0, A7
ADDL $(MACHSIZE-4), A7 /* start stack under machine struct */
MOVL $0, u(SB)
MOVL $vectors(SB), A0
MOVL A0, VBR
BSR main(SB)
/* never returns */
dead:
BRA dead
/*
* Take first processor into user mode. Leave enough room on the stack
* for a full-sized Ureg (including long bus error format) to fit
*/
TEXT touser(SB), $-4
MOVL $(USERADDR+BY2PG-UREGVARSZ), A7
MOVW $0, -(A7)
MOVL $(UTZERO+32), -(A7) /* header is in text */
MOVW $0, -(A7)
MOVL $(USTKTOP-6*BY2WD), A0 /* MAXSYSARG=6 */
MOVL A0, USP
MOVW $(SUPER|SPL(0)), SR
MOVL $8, R0
MOVL R0, CACR
RTE
TEXT firmware(SB), $0
MOVL $0x40000090, A0
JMP (A0)
TEXT splhi(SB), $0
MOVL m(SB), A0
MOVL (A7), 4(A0)
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(7)), SR
RTS
TEXT splduart(SB), $0
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(5)), SR
RTS
TEXT spllo(SB), $0
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(0)), SR
RTS
TEXT splx(SB), $0
MOVL sr+0(FP), R0
MOVW R0, SR
RTS
TEXT spldone(SB), $0
RTS
TEXT spl1(SB), $0
MOVL $0, R0
MOVW SR, R0
MOVW $(SUPER|SPL(1)), SR
RTS
TEXT flushcpucache(SB), $0
MOVL $(CCLEAR|CENABLE), R0
MOVL R0, CACR
RTS
TEXT cacrtrap(SB), $0 /* user entry point to control cache, e.g. flush */
MOVL R0, CACR
RTE
TEXT setlabel(SB), $0
MOVL sr+0(FP), A0
MOVL A7, (A0)+ /* stack pointer */
MOVL (A7), (A0)+ /* pc of caller */
MOVW SR, (A0)+ /* status register */
CLRL R0 /* ret 0 => not returning */
RTS
TEXT gotolabel(SB), $0
MOVL p+0(FP), A0
MOVW $(SUPER|SPL(7)), SR
MOVL (A0)+, A7 /* stack pointer */
MOVL (A0)+, (A7) /* pc; stuff into stack frame */
MOVW (A0)+, R0 /* status register */
MOVW R0, SR
MOVL $1, R0 /* ret 1 => returning */
RTS
/*
* Test and set, as a subroutine
*/
TEXT tas(SB), $0
MOVL $0, R0
MOVL a+0(FP), A0
TAS (A0)
BEQ tas_1
MOVL $1, R0
tas_1:
RTS
/*
* Floating point
*/
TEXT fpsave(SB), $0
FSAVE (fp+0(FP))
RTS
TEXT fprestore(SB), $0
FRESTORE (fp+0(FP))
RTS
TEXT fpregsave(SB), $0
FMOVEM $0xFF, (3*4)(fr+0(FP))
FMOVEMC $0x7, (fr+0(FP))
RTS
TEXT fpregrestore(SB), $0
FMOVEMC (fr+0(FP)), $0x7
FMOVEM (3*4)(fr+0(FP)), $0xFF
RTS
TEXT fpcr(SB), $0
MOVL new+0(FP), R1
MOVL FPCR, R0
MOVL R1, FPCR
RTS
TEXT rfnote(SB), $0
MOVL uregp+0(FP), A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1+1)*BY2WD), A7
RTE
TEXT illegal(SB), $0
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR trap(SB)
ADDL $4, A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1)*BY2WD+BY2WD), A7
RTE
TEXT systrap(SB), $0
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVL A6, ((8+6)*BY2WD)(A7)
MOVL R0, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR syscall(SB)
MOVL ((1+8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVL ((1+8+6)*BY2WD)(A7), A6
ADDL $((1+8+8+1)*BY2WD+BY2WD), A7
RTE
TEXT buserror(SB), $0
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
PEA ((8+8+1+3)*BY2WD)(A7)
PEA 4(A7)
BSR fault68020(SB)
ADDL $8, A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1)*BY2WD+BY2WD), A7
RTE
TEXT tacintr(SB), $0 /* level 1 */
MOVL R0, -(A7)
MOVL TACADDR, R0
MOVL (A7)+, R0
RTE
TEXT portintr(SB), $0 /* level 2 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR devportintr(SB)
BRA retintr
TEXT dkintr(SB), $0 /* level 3 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR inconintr(SB)
BRA retintr
TEXT mouseintr(SB), $0 /* level 4 */
MOVEM $0x80C2, -(A7) /* D0, A0, A1, A6 */
MOVL $a6base(SB), A6
MOVL $15, R0 /* mask off hex switch */
ANDB MOUSE,R0 /* clears quadrature interrupt */
LEA mousetab(SB)(R0.W*8), A0
LEA mouse(SB), A1
MOVL (A0)+, R0
ADDL R0, (A1)+ /* dx */
MOVL (A0), R0
ADDL R0, (A1)+ /* dy */
ADDL $1, (A1) /* track */
MOVEM (A7)+, $0x4301
RTE
TEXT uartintr(SB), $0 /* level 5 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR duartintr(SB)
BRA retintr
TEXT syncintr(SB), $0 /* level 6 */
MOVL $DBMAGIC, -(A7)
SUBL $((8+8+1)*BY2WD), A7
MOVEM $0x7FFF, (A7)
MOVL $a6base(SB), A6
MOVL USP, A0
MOVL A0, ((8+8)*BY2WD)(A7)
MOVL A7, -(A7)
BSR clock(SB)
/* fall through */
retintr:
BSR mousetry(SB)
ADDL $4, A7
MOVL ((8+8)*BY2WD)(A7), A0
MOVL A0, USP
MOVEM (A7), $0x7FFF
ADDL $((8+8+1)*BY2WD+BY2WD), A7
RTE
GLOBL duarttimer+0(SB),$4
TEXT duartreadtimer+0(SB), $0
MOVW SR, R1 /* spl7() */
MOVW $0x2700, SR
MOVL $0x40100000, A0
CLRL R0
TSTB 15(A0) /* stop timer */
MOVW 6(A0), R0 /* read hi,lo */
TSTB 14(A0) /* restart timer */
NOTW R0 /* timer counts down from 0xffff */
ADDL duarttimer(SB), R0
MOVL R0, duarttimer(SB)
MOVW R1, SR
RTS
GLOBL mousetab(SB), $128
DATA mousetab+ 0(SB)/4, -1 /* x down, */
DATA mousetab+ 4(SB)/4, 1 /* y up */
DATA mousetab+ 8(SB)/4, 0 /* x - */
DATA mousetab+ 12(SB)/4, 1 /* y up */
DATA mousetab+ 16(SB)/4, 1 /* x up */
DATA mousetab+ 20(SB)/4, 1 /* y up */
DATA mousetab+ 24(SB)/4, 0 /* x - */
DATA mousetab+ 28(SB)/4, 1 /* y up */
DATA mousetab+ 32(SB)/4, -1 /* x down */
DATA mousetab+ 36(SB)/4, 0 /* y - */
DATA mousetab+ 40(SB)/4, 0 /* x - */
DATA mousetab+ 44(SB)/4, 0 /* y - */
DATA mousetab+ 48(SB)/4, 1 /* x up, */
DATA mousetab+ 52(SB)/4, 0 /* y - */
DATA mousetab+ 56(SB)/4, 0 /* x - */
DATA mousetab+ 60(SB)/4, 0 /* y - */
DATA mousetab+ 64(SB)/4, -1 /* x down */
DATA mousetab+ 68(SB)/4, -1 /* y down */
DATA mousetab+ 72(SB)/4, 0 /* x - */
DATA mousetab+ 76(SB)/4, -1 /* y down */
DATA mousetab+ 80(SB)/4, 1 /* x up */
DATA mousetab+ 84(SB)/4, -1 /* y down */
DATA mousetab+ 88(SB)/4, 0 /* x - */
DATA mousetab+ 92(SB)/4, -1 /* y down */
DATA mousetab+ 96(SB)/4, -1 /* x down */
DATA mousetab+100(SB)/4, 0 /* y - */
DATA mousetab+104(SB)/4, 0 /* x - */
DATA mousetab+108(SB)/4, 0 /* y - */
DATA mousetab+112(SB)/4, 1 /* x up */
DATA mousetab+116(SB)/4, 0 /* y - */
DATA mousetab+120(SB)/4, 0 /* x - */
DATA mousetab+124(SB)/4, 0 /* y - */
GLOBL mach0+0(SB), $MACHSIZE
GLOBL u(SB), $4
GLOBL m(SB), $4

38
sys/src/cmd/5a/l.s
View file

@ -1,38 +0,0 @@
TEXT main(SB), $0
ADD R1,R4
ADD R1,R3,R4
ADD R1<<1,R3,R4 /* logical left */
ADD R1>>1,R3,R4 /* logical right */
ADD R1->1,R3,R4 /* arithmetic right */
ADD R1@>1,R3,R4 /* rotate right */
ADD R1<<R2,R3,R4
ADD $10,R1,R4
loop:
ADD.S.NE R1,R4
BNE loop
MOVW R3, CPSR
MOVW R3, SPSR
MOVW R3, F10
MOVW R3, (R2)
MOVW R3, 10(R2)
MOVW R3, name(SB)
MOVW R3, name(SB)(R2)
MOVW R3, name(SB)(R2)
MOVW R3, (R2)
MOVW R3, R1<<2(R2)
MRC.EQ 3,9,R3,C5,C6,2
MRC 3,9,R3,C5,C6,2
MOVM.IA [R0,SP,R4], (R2)
MOVM.DB.W (R0), [R6-R11]
MOVM.DB.W (R0), [R0-R11]
MOVM.S (R0), [R0-R11] // .S is supervisor space
CMN $4096,R0,
RET

31
sys/src/cmd/5l/l.s
View file

@ -1,31 +0,0 @@
TEXT main(SB), $0
ADD R1,R4
ADD R1,R3,R4
ADD R1<<1,R3,R4 /* logical left */
ADD R1>>1,R3,R4 /* logical right */
ADD R1->1,R3,R4 /* arithmetic right */
ADD R1@>1,R3,R4 /* rotate right */
ADD R1<<R2,R3,R4
MOVW R1<<R2,R4
ADD $10,R1,R4
loop:
ADD.S.NE R1,R4
BNE loop
MRC.EQ 3,9,R3,C5,C6,2
MRC 3,9,R3,C5,C6,2
MOVW $(0xf<<28), CPSR
MOVW.F R3, SPSR
SWI 123
SWPW R1,(R2),R3
SWPBU.NE (R2),R3
SWPBU R1,(R2)
MOVM.IA.S.W (R13),[R15]
RFE

704
sys/src/cmd/8a/l.s
View file

@ -1,704 +0,0 @@
/*
* Memory and machine-specific definitions. Used in C and assembler.
*/
/*
* Sizes
*/
#define BI2BY 8 /* bits per byte */
#define BI2WD 32 /* bits per word */
#define BY2WD 4 /* bytes per word */
#define BY2PG 4096 /* bytes per page */
#define WD2PG (BY2PG/BY2WD) /* words per page */
#define PGSHIFT 12 /* log(BY2PG) */
#define PGROUND(s) (((s)+(BY2PG-1))&~(BY2PG-1))
#define MAXMACH 1 /* max # cpus system can run */
/*
* Time
*/
#define HZ (20) /* clock frequency */
#define MS2HZ (1000/HZ) /* millisec per clock tick */
#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
#define TK2MS(t) ((((ulong)(t))*1000)/HZ) /* ticks to milliseconds */
#define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */
/*
* Fundamental addresses
*/
/*
* Address spaces
*
* User is at 0-2GB
* Kernel is at 2GB-4GB
*
* To avoid an extra page map, both the user stack (USTKTOP) and
* the temporary user stack (TSTKTOP) should be in the the same
* 4 meg.
*/
#define UZERO 0 /* base of user address space */
#define UTZERO (UZERO+BY2PG) /* first address in user text */
#define KZERO 0x80000000 /* base of kernel address space */
#define KTZERO KZERO /* first address in kernel text */
#define USERADDR 0xC0000000 /* struct User */
#define UREGADDR (USERADDR+BY2PG-4*19)
#define TSTKTOP USERADDR /* end of new stack in sysexec */
#define TSTKSIZ 10
#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
#define USTKSIZE (16*1024*1024 - TSTKSIZ*BY2PG) /* size of user stack */
#define ROMBIOS (KZERO|0xF0000)
#define MACHSIZE 4096
#define isphys(x) (((ulong)x)&KZERO)
/*
* known 80386 segments (in GDT) and their selectors
*/
#define NULLSEG 0 /* null segment */
#define KDSEG 1 /* kernel data/stack */
#define KESEG 2 /* kernel executable */
#define UDSEG 3 /* user data/stack */
#define UESEG 4 /* user executable */
#define TSSSEG 5 /* task segment */
#define SELGDT (0<<3) /* selector is in gdt */
#define SELLDT (1<<3) /* selector is in ldt */
#define SELECTOR(i, t, p) (((i)<<3) | (t) | (p))
#define NULLSEL SELECTOR(NULLSEG, SELGDT, 0)
#define KESEL SELECTOR(KESEG, SELGDT, 0)
#define KDSEL SELECTOR(KDSEG, SELGDT, 0)
#define UESEL SELECTOR(UESEG, SELGDT, 3)
#define UDSEL SELECTOR(UDSEG, SELGDT, 3)
#define TSSSEL SELECTOR(TSSSEG, SELGDT, 0)
/*
* fields in segment descriptors
*/
#define SEGDATA (0x10<<8) /* data/stack segment */
#define SEGEXEC (0x18<<8) /* executable segment */
#define SEGTSS (0x9<<8) /* TSS segment */
#define SEGCG (0x0C<<8) /* call gate */
#define SEGIG (0x0E<<8) /* interrupt gate */
#define SEGTG (0x0F<<8) /* task gate */
#define SEGTYPE (0x1F<<8)
#define SEGP (1<<15) /* segment present */
#define SEGPL(x) ((x)<<13) /* priority level */
#define SEGB (1<<22) /* granularity 1==4k (for expand-down) */
#define SEGG (1<<23) /* granularity 1==4k (for other) */
#define SEGE (1<<10) /* expand down */
#define SEGW (1<<9) /* writable (for data/stack) */
#define SEGR (1<<9) /* readable (for code) */
#define SEGD (1<<22) /* default 1==32bit (for code) */
/*
* virtual MMU
*/
#define PTEMAPMEM (1024*1024) /* ??? */
#define SEGMAPSIZE 16 /* ??? */
#define PTEPERTAB (PTEMAPMEM/BY2PG) /* ??? */
#define PPN(x) ((x)&~(BY2PG-1))
/*
* physical MMU
*/
#define PTEVALID (1<<0)
#define PTEUNCACHED 0 /* everything is uncached */
#define PTEWRITE (1<<1)
#define PTERONLY (0<<1)
#define PTEKERNEL (0<<2)
#define PTEUSER (1<<2)
/*
* flag register bits that we care about
*/
#define IFLAG 0x200
#define OP16 BYTE $0x66
/*
* about to walk all over ms/dos - turn off interrupts
*/
TEXT origin(SB),$0
CLI
#ifdef BOOT
/*
* This part of l.s is used only in the boot kernel.
* It assumes that we are in real address mode, i.e.,
* that we look like an 8086.
*/
/*
* relocate everything to a half meg and jump there
* - looks wierd because it is being assembled by a 32 bit
* assembler for a 16 bit world
*/
MOVL $0,BX
INCL BX
SHLL $15,BX
MOVL BX,CX
MOVW BX,ES
MOVL $0,SI
MOVL SI,DI
CLD; REP; MOVSL
/* JMPFAR 0X8000:$lowcore(SB) /**/
BYTE $0xEA
WORD $lowcore(SB)
WORD $0X8000
TEXT lowcore(SB),$0
/*
* now that we're in low core, update the DS
*/
MOVW BX,DS
/*
* goto protected mode
*/
/* MOVL tgdtptr(SB),GDTR /**/
BYTE $0x0f
BYTE $0x01
BYTE $0x16
WORD $tgdtptr(SB)
MOVL CR0,AX
ORL $1,AX
MOVL AX,CR0
/*
* clear prefetch queue (wierd code to avoid optimizations)
*/
CLC
JCC flush
MOVL AX,AX
flush:
/*
* set all segs
*/
/* MOVW $SELECTOR(1, SELGDT, 0),AX /**/
BYTE $0xc7
BYTE $0xc0
WORD $SELECTOR(1, SELGDT, 0)
MOVW AX,DS
MOVW AX,SS
MOVW AX,ES
MOVW AX,FS
MOVW AX,GS
/* JMPFAR SELECTOR(2, SELGDT, 0):$mode32bit(SB) /**/
BYTE $0x66
BYTE $0xEA
LONG $mode32bit-KZERO(SB)
WORD $SELECTOR(2, SELGDT, 0)
TEXT mode32bit(SB),$0
#endif BOOT
/*
* Clear BSS
*/
LEAL edata-KZERO(SB),SI
MOVL SI,DI
ADDL $4,DI
MOVL $0,AX
MOVL AX,(SI)
LEAL end-KZERO(SB),CX
SUBL DI,CX
SHRL $2,CX
CLD; REP; MOVSL
/*
* make a bottom level page table page that maps the first
* 16 meg of physical memory
*/
LEAL tpt-KZERO(SB),AX /* get phys addr of temporary page table */
ADDL $(BY2PG-1),AX /* must be page aligned */
ANDL $(~(BY2PG-1)),AX /* ... */
MOVL $(4*1024),CX /* pte's per page */
MOVL $((((4*1024)-1)<<PGSHIFT)|PTEVALID|PTEKERNEL|PTEWRITE),BX
setpte:
MOVL BX,-4(AX)(CX*4)
SUBL $(1<<PGSHIFT),BX
LOOP setpte
/*
* make a top level page table page that maps the first
* 16 meg of memory to 0 thru 16meg and to KZERO thru KZERO+16meg
*/
MOVL AX,BX
ADDL $(4*BY2PG),AX
ADDL $(PTEVALID|PTEKERNEL|PTEWRITE),BX
MOVL BX,0(AX)
MOVL BX,((((KZERO>>1)&0x7FFFFFFF)>>(2*PGSHIFT-1-4))+0)(AX)
ADDL $BY2PG,BX
MOVL BX,4(AX)
MOVL BX,((((KZERO>>1)&0x7FFFFFFF)>>(2*PGSHIFT-1-4))+4)(AX)
ADDL $BY2PG,BX
MOVL BX,8(AX)
MOVL BX,((((KZERO>>1)&0x7FFFFFFF)>>(2*PGSHIFT-1-4))+8)(AX)
ADDL $BY2PG,BX
MOVL BX,12(AX)
MOVL BX,((((KZERO>>1)&0x7FFFFFFF)>>(2*PGSHIFT-1-4))+12)(AX)
/*
* point processor to top level page & turn on paging
*/
MOVL AX,CR3
MOVL CR0,AX
ORL $0X80000000,AX
ANDL $~(0x8|0x2),AX /* TS=0, MP=0 */
MOVL AX,CR0
/*
* use a jump to an absolute location to get the PC into
* KZERO.
*/
LEAL tokzero(SB),AX
JMP* AX
TEXT tokzero(SB),$0
/*
* stack and mach
*/
MOVL $mach0(SB),SP
MOVL SP,m(SB)
MOVL $0,0(SP)
ADDL $(MACHSIZE-4),SP /* start stack under machine struct */
MOVL $0, u(SB)
/*
* clear flags
*/
MOVL $0,AX
PUSHL AX
POPFL
CALL main(SB)
loop:
JMP loop
GLOBL mach0+0(SB), $MACHSIZE
GLOBL u(SB), $4
GLOBL m(SB), $4
GLOBL tpt(SB), $(BY2PG*6)
/*
* gdt to get us to 32-bit/segmented/unpaged mode
*/
TEXT tgdt(SB),$0
/* null descriptor */
LONG $0
LONG $0
/* data segment descriptor for 4 gigabytes (PL 0) */
LONG $(0xFFFF)
LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
/* exec segment descriptor for 4 gigabytes (PL 0) */
LONG $(0xFFFF)
LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
/*
* pointer to initial gdt
*/
TEXT tgdtptr(SB),$0
WORD $(3*8)
LONG $tgdt-KZERO(SB)
/*
* input a byte
*/
TEXT inb(SB),$0
MOVL p+0(FP),DX
XORL AX,AX
INB
RET
/*
* output a byte
*/
TEXT outb(SB),$0
MOVL p+0(FP),DX
MOVL b+4(FP),AX
OUTB
RET
/*
* input a string of shorts from a port
*/
TEXT inss(SB),$0
MOVL p+0(FP),DX
MOVL a+4(FP),DI
MOVL c+8(FP),CX
CLD; REP; OP16; INSL
RET
/*
* output a string of shorts to a port
*/
TEXT outss(SB),$0
MOVL p+0(FP),DX
MOVL a+4(FP),SI
MOVL c+8(FP),CX
CLD; REP; OP16; OUTSL
RET
/*
* test and set
*/
TEXT tas(SB),$0
MOVL $0xdeadead,AX
MOVL l+0(FP),BX
XCHGL AX,(BX)
RET
/*
* routines to load/read various system registers
*/
GLOBL idtptr(SB),$6
TEXT putidt(SB),$0 /* interrupt descriptor table */
MOVL t+0(FP),AX
MOVL AX,idtptr+2(SB)
MOVL l+4(FP),AX
MOVW AX,idtptr(SB)
MOVL idtptr(SB),IDTR
RET
GLOBL gdtptr(SB),$6
TEXT putgdt(SB),$0 /* global descriptor table */
MOVL t+0(FP),AX
MOVL AX,gdtptr+2(SB)
MOVL l+4(FP),AX
MOVW AX,gdtptr(SB)
MOVL gdtptr(SB),GDTR
RET
TEXT putcr3(SB),$0 /* top level page table pointer */
MOVL t+0(FP),AX
MOVL AX,CR3
RET
TEXT puttr(SB),$0 /* task register */
MOVL t+0(FP),AX
MOVW AX,TASK
RET
TEXT getcr0(SB),$0 /* coprocessor bits */
MOVL CR0,AX
RET
TEXT getcr2(SB),$0 /* fault address */
MOVL CR2,AX
RET
#define FPOFF\
WAIT;\
MOVL CR0,AX;\
ORL $0x4,AX /* EM=1 */;\
MOVL AX,CR0
#define FPON\
MOVL CR0,AX;\
ANDL $~0x4,AX /* EM=0 */;\
MOVL AX,CR0
TEXT fpoff(SB),$0 /* turn off floating point */
FPOFF
RET
TEXT fpinit(SB),$0 /* turn on & init the floating point */
FPON
FINIT
WAIT
PUSHW $0x0330
FLDCW 0(SP) /* ignore underflow/precision, signal others */
POPW AX
WAIT
RET
TEXT fpsave(SB),$0 /* save floating point state and turn off */
MOVL p+0(FP),AX
WAIT
FSAVE 0(AX)
FPOFF
RET
TEXT fprestore(SB),$0 /* turn on floating point and restore regs */
FPON
MOVL p+0(FP),AX
FRSTOR 0(AX)
WAIT
RET
TEXT fpstatus(SB),$0 /* get floating point status */
FSTSW AX
RET
/*
* special traps
*/
TEXT intr0(SB),$0
PUSHL $0
PUSHL $0
JMP intrcommon
TEXT intr1(SB),$0
PUSHL $0
PUSHL $1
JMP intrcommon
TEXT intr2(SB),$0
PUSHL $0
PUSHL $2
JMP intrcommon
TEXT intr3(SB),$0
PUSHL $0
PUSHL $3
JMP intrcommon
TEXT intr4(SB),$0
PUSHL $0
PUSHL $4
JMP intrcommon
TEXT intr5(SB),$0
PUSHL $0
PUSHL $5
JMP intrcommon
TEXT intr6(SB),$0
PUSHL $0
PUSHL $6
JMP intrcommon
TEXT intr7(SB),$0
PUSHL $0
PUSHL $7
JMP intrcommon
TEXT intr8(SB),$0
PUSHL $8
JMP intrscommon
TEXT intr9(SB),$0
PUSHL $0
PUSHL $9
JMP intrcommon
TEXT intr10(SB),$0
PUSHL $10
JMP intrscommon
TEXT intr11(SB),$0
PUSHL $11
JMP intrscommon
TEXT intr12(SB),$0
PUSHL $12
JMP intrscommon
TEXT intr13(SB),$0
PUSHL $13
JMP intrscommon
TEXT intr14(SB),$0
PUSHL $14
JMP intrscommon
TEXT intr15(SB),$0
PUSHL $0
PUSHL $15
JMP intrcommon
TEXT intr16(SB),$0
PUSHL $0
PUSHL $16
JMP intrcommon
TEXT intr24(SB),$0
PUSHL $0
PUSHL $24
JMP intrcommon
TEXT intr25(SB),$0
PUSHL $0
PUSHL $25
JMP intrcommon
TEXT intr26(SB),$0
PUSHL $0
PUSHL $26
JMP intrcommon
TEXT intr27(SB),$0
PUSHL $0
PUSHL $27
JMP intrcommon
TEXT intr28(SB),$0
PUSHL $0
PUSHL $28
JMP intrcommon
TEXT intr29(SB),$0
PUSHL $0
PUSHL $29
JMP intrcommon
TEXT intr30(SB),$0
PUSHL $0
PUSHL $30
JMP intrcommon
TEXT intr31(SB),$0
PUSHL $0
PUSHL $31
JMP intrcommon
TEXT intr32(SB),$0
PUSHL $0
PUSHL $16
JMP intrcommon
TEXT intr33(SB),$0
PUSHL $0
PUSHL $33
JMP intrcommon
TEXT intr34(SB),$0
PUSHL $0
PUSHL $34
JMP intrcommon
TEXT intr35(SB),$0
PUSHL $0
PUSHL $35
JMP intrcommon
TEXT intr36(SB),$0
PUSHL $0
PUSHL $36
JMP intrcommon
TEXT intr37(SB),$0
PUSHL $0
PUSHL $37
JMP intrcommon
TEXT intr38(SB),$0
PUSHL $0
PUSHL $38
JMP intrcommon
TEXT intr39(SB),$0
PUSHL $0
PUSHL $39
JMP intrcommon
TEXT intr64(SB),$0
PUSHL $0
PUSHL $64
JMP intrcommon
TEXT intrbad(SB),$0
PUSHL $0
PUSHL $0x1ff
JMP intrcommon
intrcommon:
PUSHL DS
PUSHL ES
PUSHL FS
PUSHL GS
PUSHAL
MOVL $(KDSEL),AX
MOVW AX,DS
MOVW AX,ES
LEAL 0(SP),AX
PUSHL AX
CALL trap(SB)
POPL AX
POPAL
POPL GS
POPL FS
POPL ES
POPL DS
ADDL $8,SP /* error code and trap type */
IRETL
intrscommon:
PUSHL DS
PUSHL ES
PUSHL FS
PUSHL GS
PUSHAL
MOVL $(KDSEL),AX
MOVW AX,DS
MOVW AX,ES
LEAL 0(SP),AX
PUSHL AX
CALL trap(SB)
POPL AX
POPAL
POPL GS
POPL FS
POPL ES
POPL DS
ADDL $8,SP /* error code and trap type */
IRETL
/*
* interrupt level is interrupts on or off
*/
TEXT spllo(SB),$0
PUSHFL
POPL AX
STI
RET
TEXT splhi(SB),$0
PUSHFL
POPL AX
CLI
RET
TEXT splx(SB),$0
MOVL s+0(FP),AX
PUSHL AX
POPFL
RET
/*
* do nothing whatsoever till interrupt happens
*/
TEXT idle(SB),$0
HLT
RET
/*
* label consists of a stack pointer and a PC
*/
TEXT gotolabel(SB),$0
MOVL l+0(FP),AX
MOVL 0(AX),SP /* restore sp */
MOVL 4(AX),AX /* put return pc on the stack */
MOVL AX,0(SP)
MOVL $1,AX /* return 1 */
RET
TEXT setlabel(SB),$0
MOVL l+0(FP),AX
MOVL SP,0(AX) /* store sp */
MOVL 0(SP),BX /* store return pc */
MOVL BX,4(AX)
MOVL $0,AX /* return 0 */
RET
/*
* Used to get to the first process.
* Set up an interrupt return frame and IRET to user level.
*/
TEXT touser(SB),$0
PUSHL $(UDSEL) /* old ss */
PUSHL $(USTKTOP) /* old sp */
PUSHFL /* old flags */
PUSHL $(UESEL) /* old cs */
PUSHL $(UTZERO+32) /* old pc */
MOVL $(UDSEL),AX
MOVW AX,DS
MOVW AX,ES
MOVW AX,GS
MOVW AX,FS
IRETL
/*
* set configuration register
*/
TEXT config(SB),$0
MOVL l+0(FP),AX
MOVL $0x3F3,DX
OUTB
OUTB
RET

696
sys/src/cmd/ka/l.s
View file

@ -1,696 +0,0 @@
/*
* Memory and machine-specific definitions. Used in C and assembler.
*/
/*
* Sizes
*/
#define BI2BY 8 /* bits per byte */
#define BI2WD 32 /* bits per word */
#define BY2WD 4 /* bytes per word */
#define BY2PG 4096 /* bytes per page */
#define WD2PG (BY2PG/BY2WD) /* words per page */
#define PGSHIFT 12 /* log(BY2PG) */
#define PGROUND(s) (((s)+(BY2PG-1))&~(BY2PG-1))
#define MAXMACH 1 /* max # cpus system can run */
/*
* Time
*/
#define HZ 20 /* clock frequency */
#define MS2HZ (1000/HZ) /* millisec per clock tick */
#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
#define TK2MS(t) ((((ulong)(t))*1000)/HZ) /* ticks to milliseconds */
#define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */
/*
* PSR bits
*/
#define PSREC 0x00002000
#define PSREF 0x00001000
#define PSRSUPER 0x00000080
#define PSRPSUPER 0x00000040
#define PSRET 0x00000020
#define SPL(n) (n<<8)
/*
* Magic registers
*/
#define MACH 6 /* R6 is m-> */
#define USER 5 /* R5 is u-> */
/*
* Fundamental addresses
*/
#define USERADDR 0xE0000000
#define UREGADDR (USERADDR+BY2PG-((32+6)*BY2WD))
#define BOOTSTACK (KTZERO-0*BY2PG)
#define TRAPS (KTZERO-2*BY2PG)
/*
* MMU
*/
#define VAMASK 0x3FFFFFFF
#define NPMEG (1<<12)
#define BY2SEGM (1<<18)
#define PG2SEGM (1<<6)
#define NTLBPID (1+NCONTEXT) /* TLBPID 0 is unallocated */
#define NCONTEXT 8
#define CONTEXT 0x30000000 /* in ASI 2 */
/*
* MMU regions
*/
#define INVALIDSEGM 0xFFFC0000 /* highest seg of VA reserved as invalid */
#define INVALIDPMEG 0x7F
#define SCREENSEGM 0xFFF80000
#define SCREENPMEG 0x7E
#define ROMSEGM 0xFFE80000
#define ROMEND 0xFFEA0000
#define PG2ROM ((ROMEND-ROMSEGM)/BY2PG)
#define IOSEGM0 ROMSEGM /* see mmuinit() */
#define NIOSEGM ((SCREENSEGM-ROMSEGM)/BY2SEGM)
#define IOPMEG0 (SCREENPMEG-NIOSEGM)
#define IOSEGM ROMEND
#define IOEND SCREENSEGM
#define TOPPMEG IOPMEG0
/*
* MMU entries
*/
#define PTEVALID (1<<31)
#define PTERONLY (0<<30)
#define PTEWRITE (1<<30)
#define PTEKERNEL (1<<29)
#define PTENOCACHE (1<<28)
#define PTEMAINMEM (0<<26)
#define PTEIO (1<<26)
#define PTEACCESS (1<<25)
#define PTEMODIFY (1<<24)
#define PTEUNCACHED 0
#define PTEMAPMEM (1024*1024)
#define PTEPERTAB (PTEMAPMEM/BY2PG)
#define SEGMAPSIZE 16
#define INVALIDPTE 0
#define PPN(pa) ((pa>>12)&0xFFFF)
/*
* Weird addresses in various ASI's
*/
#define CACHETAGS 0x80000000 /* ASI 2 */
#define CACHEDATA 0x90000000 /* ASI 2 */
#define SER 0x60000000 /* ASI 2 */
#define SEVAR 0x60000004 /* ASI 2 */
#define ASER 0x60000008 /* ASI 2 */
#define ASEVAR 0x6000000C /* ASI 2 */
#define ENAB 0x40000000 /* ASI 2 */
#define ENABCACHE 0x10
#define ENABRESET 0x04
/*
* Virtual addresses
*/
#define VTAG(va) ((va>>22)&0x03F)
#define VPN(va) ((va>>13)&0x1FF)
#define PARAM ((char*)0x40500000)
#define TLBFLUSH_ 0x01
/*
* Address spaces
*/
#define UZERO 0x00000000 /* base of user address space */
#define UTZERO (UZERO+BY2PG) /* first address in user text */
#define TSTKTOP 0x10000000 /* end of new stack in sysexec */
#define TSTKSIZ 32
#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
#define KZERO 0xE0000000 /* base of kernel address space */
#define KTZERO (KZERO+4*BY2PG) /* first address in kernel text */
#define USTKSIZE (4*1024*1024) /* size of user stack */
#define MACHSIZE 4096
#define isphys(x) (((ulong)(x)&0xF0000000) == KZERO)
#define SYSPSR (SPL(0x0)|PSREF|PSRSUPER|0)
#define NOOP OR R0, R0; OR R0, R0; OR R0, R0
TEXT start(SB), $-4
/* get virtual, fast */
/* we are executing in segment 0, mapped to pmeg 0. stack is there too */
/* get virtual by mapping segment(KZERO) to pmeg 0., and next to 1 */
MOVW $KZERO, R7
MOVB R0, (R7, 3)
MOVW $(KZERO+BY2SEGM), R7
MOVW $1, R8
MOVB R8, (R7, 3)
/* now mapped correctly. jmpl to where we want to be */
MOVW $setSB(SB), R2
MOVW $startvirt(SB), R7
JMPL (R7)
MOVW $_mul(SB), R0 /* touch _mul etc.; doesn't need to execute */
RETURN /* can't get here */
TEXT startvirt(SB), $-4
MOVW $BOOTSTACK, R1
MOVW $(SPL(0xF)|PSREF|PSRSUPER), R7
MOVW R7, PSR
MOVW $(0x35<<22), R7 /* NVM OFM DZM AU */
MOVW R7, fsr+0(SB)
MOVW fsr+0(SB), FSR
FMOVD $0.5, F26 /* 0.5 -> F26 */
FSUBD F26, F26, F24 /* 0.0 -> F24 */
FADDD F26, F26, F28 /* 1.0 -> F28 */
FADDD F28, F28, F30 /* 2.0 -> F30 */
FMOVD F24, F0
FMOVD F24, F2
FMOVD F24, F4
FMOVD F24, F6
FMOVD F24, F8
FMOVD F24, F10
FMOVD F24, F12
FMOVD F24, F14
FMOVD F24, F16
FMOVD F24, F18
FMOVD F24, F20
FMOVD F24, F22
MOVW $mach0(SB), R(MACH)
/* MOVW $0x8, R7 /**/
MOVW R0, WIM
JMPL main(SB)
MOVW (R0), R0
RETURN
TEXT swap1(SB), $0
TAS (R7), R7 /* LDSTUB, thank you ken */
RETURN
TEXT swap1_should_work(SB), $0
MOVW R7, R8
MOVW $1, R7
SWAP (R8), R7
RETURN
TEXT swap1x(SB), $0
MOVW PSR, R9
MOVW R9, R10
AND $~PSRET, R10 /* BUG: book says this is buggy */
MOVW R10, PSR
NOOP
MOVW (R7), R7
CMP R7, R0
BNE was1
MOVW $1, R10
MOVW R10, (R8)
was1:
MOVW R9, PSR
RETURN
TEXT spllo(SB), $0
MOVW PSR, R7
MOVW R7, R10
OR $PSRET, R10
MOVW R10, PSR
NOOP
RETURN
TEXT splhi(SB), $0
MOVW R15, 4(R(MACH)) /* save PC in m->splpc */
MOVW PSR, R7
MOVW R7, R10
AND $~PSRET, R10 /* BUG: book says this is buggy */
MOVW R10, PSR
NOOP
RETURN
TEXT splx(SB), $0
MOVW R15, 4(R(MACH)) /* save PC in m->splpc */
MOVW R7, PSR /* BUG: book says this is buggy */
NOOP
RETURN
TEXT spldone(SB), $0
RETURN
TEXT touser(SB), $0
MOVW $(SYSPSR&~PSREF), R8
MOVW R8, PSR
NOOP
MOVW R7, R1
SAVE R0, R0 /* RETT is implicit RESTORE */
MOVW $(UTZERO+32), R7 /* PC; header appears in text */
MOVW $(UTZERO+32+4), R8 /* nPC */
RETT R7, R8
TEXT rfnote(SB), $0
MOVW R7, R1 /* 1st arg is &uregpointer */
ADD $4, R1 /* point at ureg */
JMP restore
TEXT traplink(SB), $-4
/* R8 to R23 are free to play with */
/* R17 contains PC, R18 contains nPC */
/* R19 has PSR loaded from vector code */
ANDCC $PSRPSUPER, R19, R0
BE usertrap
kerneltrap:
/*
* Interrupt or fault from kernel
*/
ANDN $7, R1, R20 /* dbl aligned */
MOVW R1, (0-(4*(32+6))+(4*1))(R20) /* save R1=SP */
/* really clumsy: store these in Ureg so can be restored below */
MOVW R2, (0-(4*(32+6))+(4*2))(R20) /* SB */
MOVW R5, (0-(4*(32+6))+(4*5))(R20) /* USER */
MOVW R6, (0-(4*(32+6))+(4*6))(R20) /* MACH */
SUB $(4*(32+6)), R20, R1
trap1:
MOVW Y, R20
MOVW R20, (4*(32+0))(R1) /* Y */
MOVW TBR, R20
MOVW R20, (4*(32+1))(R1) /* TBR */
AND $~0x1F, R19 /* force CWP=0 */
MOVW R19, (4*(32+2))(R1) /* PSR */
MOVW R18, (4*(32+3))(R1) /* nPC */
MOVW R17, (4*(32+4))(R1) /* PC */
MOVW R0, (4*0)(R1)
MOVW R3, (4*3)(R1)
MOVW R4, (4*4)(R1)
MOVW R7, (4*7)(R1)
RESTORE R0, R0
/* now our registers R8-R31 are same as before trap */
/* save registers two at a time */
MOVD R8, (4*8)(R1)
MOVD R10, (4*10)(R1)
MOVD R12, (4*12)(R1)
MOVD R14, (4*14)(R1)
MOVD R16, (4*16)(R1)
MOVD R18, (4*18)(R1)
MOVD R20, (4*20)(R1)
MOVD R22, (4*22)(R1)
MOVD R24, (4*24)(R1)
MOVD R26, (4*26)(R1)
MOVD R28, (4*28)(R1)
MOVD R30, (4*30)(R1)
/* SP and SB and u and m are already set; away we go */
MOVW R1, R7 /* pointer to Ureg */
SUB $8, R1
MOVW $SYSPSR, R8
MOVW R8, PSR
NOOP
JMPL trap(SB)
ADD $8, R1
restore:
MOVW (4*(32+2))(R1), R8 /* PSR */
MOVW R8, PSR
NOOP
MOVD (4*30)(R1), R30
MOVD (4*28)(R1), R28
MOVD (4*26)(R1), R26
MOVD (4*24)(R1), R24
MOVD (4*22)(R1), R22
MOVD (4*20)(R1), R20
MOVD (4*18)(R1), R18
MOVD (4*16)(R1), R16
MOVD (4*14)(R1), R14
MOVD (4*12)(R1), R12
MOVD (4*10)(R1), R10
MOVD (4*8)(R1), R8
SAVE R0, R0
MOVD (4*6)(R1), R6
MOVD (4*4)(R1), R4
MOVD (4*2)(R1), R2
MOVW (4*(32+0))(R1), R20 /* Y */
MOVW R20, Y
MOVW (4*(32+4))(R1), R17 /* PC */
MOVW (4*(32+3))(R1), R18 /* nPC */
MOVW (4*1)(R1), R1 /* restore R1=SP */
RETT R17, R18
usertrap:
/*
* Interrupt or fault from user
*/
MOVW R1, R8
MOVW R2, R9
MOVW $setSB(SB), R2
MOVW $(USERADDR+BY2PG), R1
MOVW R8, (0-(4*(32+6))+(4*1))(R1) /* save R1=SP */
MOVW R9, (0-(4*(32+6))+(4*2))(R1) /* save R2=SB */
MOVW R5, (0-(4*(32+6))+(4*5))(R1) /* save R5=USER */
MOVW R6, (0-(4*(32+6))+(4*6))(R1) /* save R6=MACH */
MOVW $USERADDR, R(USER)
MOVW $mach0(SB), R(MACH)
SUB $(4*(32+6)), R1
JMP trap1
TEXT syslink(SB), $-4
/* R8 to R23 are free to play with */
/* R17 contains PC, R18 contains nPC */
/* R19 has PSR loaded from vector code */
/* assume user did it; syscall checks */
MOVW R1, R8
MOVW R2, R9
MOVW $setSB(SB), R2
MOVW $(USERADDR+BY2PG), R1
MOVW R8, (0-(4*(32+6))+4)(R1) /* save R1=SP */
SUB $(4*(32+6)), R1
MOVW R9, (4*2)(R1) /* save R2=SB */
MOVW R3, (4*3)(R1) /* global register */
MOVD R4, (4*4)(R1) /* global register, R5=USER */
MOVD R6, (4*6)(R1) /* save R6=MACH, R7=syscall# */
MOVW $USERADDR, R(USER)
MOVW $mach0(SB), R(MACH)
MOVW TBR, R20
MOVW R20, (4*(32+1))(R1) /* TBR */
AND $~0x1F, R19
MOVW R19, (4*(32+2))(R1) /* PSR */
MOVW R18, (4*(32+3))(R1) /* nPC */
MOVW R17, (4*(32+4))(R1) /* PC */
RESTORE R0, R0
/* now our registers R8-R31 are same as before trap */
MOVW R15, (4*15)(R1)
/* SP and SB and u and m are already set; away we go */
MOVW R1, R7 /* pointer to Ureg */
SUB $8, R1
MOVW $SYSPSR, R8
MOVW R8, PSR
JMPL syscall(SB)
/* R7 contains return value from syscall */
ADD $8, R1
MOVW (4*(32+2))(R1), R8 /* PSR */
MOVW R8, PSR
NOOP
MOVW (4*15)(R1), R15
SAVE R0, R0
MOVW (4*6)(R1), R6
MOVD (4*4)(R1), R4
MOVD (4*2)(R1), R2
MOVW (4*(32+4))(R1), R17 /* PC */
MOVW (4*(32+3))(R1), R18 /* nPC */
MOVW (4*1)(R1), R1 /* restore R1=SP */
RETT R17, R18
TEXT puttbr(SB), $0
MOVW R7, TBR
NOOP
RETURN
TEXT gettbr(SB), $0
MOVW TBR, R7
RETURN
TEXT r1(SB), $0
MOVW R1, R7
RETURN
TEXT getwim(SB), $0
MOVW WIM, R7
RETURN
TEXT setlabel(SB), $0
MOVW R1, (R7)
MOVW R15, 4(R7)
MOVW $0, R7
RETURN
TEXT gotolabel(SB), $0
MOVW (R7), R1
MOVW 4(R7), R15
MOVW $1, R7
RETURN
TEXT putcxsegm(SB), $0
MOVW R7, R8 /* context */
MOVW 4(FP), R9 /* segment addr */
MOVW 8(FP), R10 /* segment value */
MOVW $0xFFE80118, R7
JMPL (R7)
RETURN
TEXT getpsr(SB), $0
MOVW PSR, R7
RETURN
TEXT putcxreg(SB), $0
MOVW $CONTEXT, R8
MOVB R7, (R8, 2)
RETURN
TEXT putb2(SB), $0
MOVW 4(FP), R8
MOVB R8, (R7, 2)
RETURN
TEXT getb2(SB), $0
MOVB (R7, 2), R7
RETURN
TEXT getw2(SB), $0
MOVW (R7, 2), R7
RETURN
TEXT putw2(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 2)
RETURN
TEXT putw4(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 4)
RETURN
TEXT getw4(SB), $0
MOVW (R7, 4), R7
RETURN
TEXT putwC(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 0xC)
RETURN
TEXT putwD(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 0xD)
RETURN
TEXT putwD16(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
ADD $(1<<4), R7
MOVW R8, (R7, 0xD)
RETURN
TEXT putwE(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 0xE)
RETURN
TEXT putwE16(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
ADD $(1<<4), R7
MOVW R8, (R7, 0xE)
RETURN
TEXT putsegm(SB), $0
MOVW 4(FP), R8
MOVW R8, (R7, 3)
RETURN
/*
* in savefpregs and restfpregs, incoming R7 points to doubleword
* below where F0 will go; doubleword align in and backfill FSR
*/
TEXT savefpregs(SB), $0
ADD $8, R7
ANDN $7, R7 /* now MOVD-aligned */
MOVW FSR, -4(R7)
MOVD F0, (0*4)(R7)
MOVD F2, (2*4)(R7)
MOVD F4, (4*4)(R7)
MOVD F6, (6*4)(R7)
MOVD F8, (8*4)(R7)
MOVD F10, (10*4)(R7)
MOVD F12, (12*4)(R7)
MOVD F14, (14*4)(R7)
MOVD F16, (16*4)(R7)
MOVD F18, (18*4)(R7)
MOVD F20, (20*4)(R7)
MOVD F22, (22*4)(R7)
MOVD F24, (24*4)(R7)
MOVD F26, (26*4)(R7)
MOVD F28, (28*4)(R7)
MOVD F30, (30*4)(R7)
MOVW PSR, R8
ANDN $PSREF, R8
MOVW R8, PSR
RETURN
TEXT restfpregs(SB), $0
MOVW PSR, R8
OR $PSREF, R8
MOVW R8, PSR
ADD $8, R7
ANDN $7, R7 /* now MOVD-aligned */
OR R0, R0
MOVW -4(R7), FSR
MOVD (0*4)(R7), F0
MOVD (2*4)(R7), F2
MOVD (4*4)(R7), F4
MOVD (6*4)(R7), F6
MOVD (8*4)(R7), F8
MOVD (10*4)(R7), F10
MOVD (12*4)(R7), F12
MOVD (14*4)(R7), F14
MOVD (16*4)(R7), F16
MOVD (18*4)(R7), F18
MOVD (20*4)(R7), F20
MOVD (22*4)(R7), F22
MOVD (24*4)(R7), F24
MOVD (26*4)(R7), F26
MOVD (28*4)(R7), F28
MOVD (30*4)(R7), F30
ANDN $PSREF, R8
MOVW R8, PSR
RETURN
TEXT clearfpintr(SB), $0
MOVW $fpq+BY2WD(SB), R7
ANDN $0x7, R7 /* must be D aligned */
MOVW $fsr+0(SB), R9
clrq:
MOVD FQ, (R7)
MOVW FSR, (R9)
MOVW (R9), R8
AND $(1<<13), R8 /* queue not empty? */
BNE clrq
RETURN
TEXT getfsr(SB), $0
MOVW $fsr+0(SB), R7
MOVW FSR, (R7)
MOVW (R7), R7
RETURN
GLOBL mach0+0(SB), $MACHSIZE
GLOBL fpq+0(SB), $(3*BY2WD)
GLOBL fsr+0(SB), $BY2WD

703
sys/src/cmd/va/l.s
View file

@ -1,703 +0,0 @@
/*
* Memory and machine-specific definitions. Used in C and assembler.
*/
/*
* Sizes
*/
#define BI2BY 8 /* bits per byte */
#define BI2WD 32 /* bits per word */
#define BY2WD 4 /* bytes per word */
#define BY2PG 4096 /* bytes per page */
#define WD2PG (BY2PG/BY2WD) /* words per page */
#define PGSHIFT 12 /* log(BY2PG) */
#define MAXMACH 4 /* max # cpus system can run */
/*
* Time
*/
#define MS2HZ 50 /* millisec per clock tick */
#define TK2SEC(t) ((t)/20) /* ticks to seconds */
#define TK2MS(t) ((t)*MS2HZ) /* ticks to milliseconds */
#define MS2TK(t) ((t)/MS2HZ) /* milliseconds to ticks */
/*
* CP0 registers
*/
#define INDEX 0
#define RANDOM 1
#define TLBPHYS 2
#define CONTEXT 4
#define BADVADDR 8
#define TLBVIRT 10
#define STATUS 12
#define CAUSE 13
#define EPC 14
#define PRID 15
/*
* M(STATUS) bits
*/
#define IEC 0x00000001
#define KUC 0x00000002
#define IEP 0x00000004
#define KUP 0x00000008
#define INTMASK 0x0000ff00
#define SW0 0x00000100
#define SW1 0x00000200
#define INTR0 0x00000400
#define INTR1 0x00000800
#define INTR2 0x00001000
#define INTR3 0x00002000
#define INTR4 0x00004000
#define INTR5 0x00008000
#define ISC 0x00010000
#define SWC 0x00020000
#define CU1 0x20000000
/*
* Traps
*/
#define UTLBMISS (KSEG0+0x00)
#define EXCEPTION (KSEG0+0x80)
/*
* Magic registers
*/
#define MACH 25 /* R25 is m-> */
#define USER 24 /* R24 is u-> */
#define MPID 0xBF000000 /* long; low 3 bits identify mp bus slot */
#define WBFLUSH 0xBC000000 /* D-CACHE data; used for write buffer flush */
/*
* Fundamental addresses
*/
#define MACHADDR 0x80014000
#define USERADDR 0xC0000000
#define UREGADDR (USERADDR+BY2PG-4-0xA0)
/*
* MMU
*/
#define KUSEG 0x00000000
#define KSEG0 0x80000000
#define KSEG1 0xA0000000
#define KSEG2 0xC0000000
#define KSEGM 0xE0000000 /* mask to check which seg */
#define PTEGLOBL (1<<8)
#define PTEVALID (1<<9)
#define PTEWRITE (1<<10)
#define PTEPID(n) ((n)<<6)
#define NTLBPID 64 /* number of pids */
#define NTLB 64 /* number of entries */
#define TLBROFF 8 /* offset of first randomly indexed entry */
/*
* Address spaces
*/
#define UZERO KUSEG /* base of user address space */
#define UTZERO (UZERO+BY2PG) /* first address in user text */
#define USTKTOP KZERO /* byte just beyond user stack */
#define TSTKTOP (USERADDR+100*BY2PG) /* top of temporary stack */
#define KZERO KSEG0 /* base of kernel address space */
#define KTZERO (KSEG0+0x20000) /* first address in kernel text */
#define USTACKSIZE (4*1024*1024) /* size of user stack */
/*
* Exception codes
*/
#define CINT 0 /* external interrupt */
#define CTLBM 1 /* TLB modification */
#define CTLBL 2 /* TLB miss (load or fetch) */
#define CTLBS 3 /* TLB miss (store) */
#define CADREL 4 /* address error (load or fetch) */
#define CADRES 5 /* address error (store) */
#define CBUSI 6 /* bus error (fetch) */
#define CBUSD 7 /* bus error (data load or store) */
#define CSYS 8 /* system call */
#define CBRK 9 /* breakpoint */
#define CRES 10 /* reserved instruction */
#define CCPU 11 /* coprocessor unusable */
#define COVF 12 /* arithmetic overflow */
#define CUNK13 13 /* undefined 13 */
#define CUNK14 14 /* undefined 14 */
#define CUNK15 15 /* undefined 15 */
#define NSEG 5
#define SP R29
#define PROM (KSEG1+0x1FC00000)
#define NOOP NOR R0,R0
#define WAIT NOOP; NOOP
/*
* Boot first processor
* - why is the processor number loaded from R0 ?????
*/
TEXT start(SB), $-4
MOVW $setR30(SB), R30
MOVW $(CU1|INTR5|INTR4|INTR3|INTR2|INTR1|SW1|SW0), R1
MOVW R1, M(STATUS)
WAIT
MOVW $(0x1C<<7), R1
MOVW R1, FCR31 /* permit only inexact and underflow */
NOOP
MOVD $0.5, F26
SUBD F26, F26, F24
ADDD F26, F26, F28
ADDD F28, F28, F30
MOVD F24, F0
MOVD F24, F2
MOVD F24, F4
MOVD F24, F6
MOVD F24, F8
MOVD F24, F10
MOVD F24, F12
MOVD F24, F14
MOVD F24, F16
MOVD F24, F18
MOVD F24, F20
MOVD F24, F22
MOVW $MACHADDR, R(MACH)
ADDU $(BY2PG-4), R(MACH), SP
MOVW $0, R(USER)
MOVW R0, 0(R(MACH))
MOVW $edata(SB), R1
MOVW $end(SB), R2
clrbss:
MOVB $0, (R1)
ADDU $1, R1
BNE R1, R2, clrbss
MOVW R4, _argc(SB)
MOVW R5, _argv(SB)
MOVW R6, _env(SB)
JAL main(SB)
JMP (R0)
/*
* Take first processor into user mode
* - argument is stack pointer to user
*/
TEXT touser(SB), $-4
MOVW M(STATUS), R1
OR $(KUP|IEP), R1
MOVW R1, M(STATUS)
NOOP
MOVW 0(FP), SP
MOVW $(UTZERO+32), R26 /* header appears in text */
RFE (R26)
/*
* Bring subsequent processors on line
*/
TEXT newstart(SB), $0
MOVW $setR30(SB), R30
MOVW $(INTR5|INTR4|INTR3|INTR2|INTR1|SW1|SW0), R1
MOVW R1, M(STATUS)
NOOP
MOVW $MACHADDR, R(MACH)
MOVB (MPID+3), R1
AND $7, R1
SLL $PGSHIFT, R1, R2
ADDU R2, R(MACH)
ADDU $(BY2PG-4), R(MACH), SP
MOVW $0, R(USER)
MOVW R1, 0(R(MACH))
JAL online(SB)
JMP (R0)
TEXT firmware(SB), $0
MOVW $(PROM+0x18), R1 /**/
/* MOVW $(PROM+0x00), R1 /**/
JMP (R1)
TEXT splhi(SB), $0
MOVW M(STATUS), R1
AND $~IEC, R1, R2
MOVW R2, M(STATUS)
NOOP
RET
TEXT spllo(SB), $0
MOVW M(STATUS), R1
OR $IEC, R1, R2
MOVW R2, M(STATUS)
NOOP
RET
TEXT splx(SB), $0
MOVW 0(FP), R1
MOVW M(STATUS), R2
AND $IEC, R1
AND $~IEC, R2
OR R2, R1
MOVW R1, M(STATUS)
NOOP
RET
TEXT wbflush(SB), $-4
MOVW $WBFLUSH, R1
MOVW 0(R1), R1
RET
TEXT setlabel(SB), $0
MOVW 0(FP), R2
MOVW $0, R1
MOVW R31, 0(R2)
MOVW R29, 4(R2)
RET
TEXT gotolabel(SB), $0
MOVW 0(FP), R2
MOVW $1, R1
MOVW 0(R2), R31
MOVW 4(R2), R29
RET
TEXT gotopc(SB), $8
MOVW 0(FP), R7 /* save arguments for later */
MOVW _argc(SB), R4
MOVW _argv(SB), R5
MOVW _env(SB), R6
MOVW R0, 4(SP)
MOVW $(64*1024), R1
MOVW R1, 8(SP)
JAL icflush(SB)
JMP (R7)
TEXT puttlb(SB), $4
JAL splhi(SB)
MOVW 0(FP), R2
MOVW 4(FP), R3
MOVW R1, 4(SP)
MOVW R2, M(TLBVIRT)
MOVW R3, M(TLBPHYS)
NOOP
TLBP
NOOP
MOVW M(INDEX), R4
BGEZ R4, index
TLBWR
NOOP
JAL splx(SB)
RET
index:
TLBWI
NOOP
JAL splx(SB)
RET
TEXT puttlbx(SB), $0
MOVW 0(FP), R4
MOVW 4(FP), R2
MOVW 8(FP), R3
SLL $8, R4
MOVW R2, M(TLBVIRT)
MOVW R3, M(TLBPHYS)
MOVW R4, M(INDEX)
NOOP
TLBWI
NOOP
RET
TEXT tlbp(SB), $0
TLBP
NOOP
MOVW M(INDEX), R1
RET
TEXT tlbvirt(SB), $0
TLBP
NOOP
MOVW M(TLBVIRT), R1
RET
TEXT gettlb(SB), $0
MOVW 0(FP), R3
MOVW 4(FP), R4
SLL $8, R3
MOVW R3, M(INDEX)
NOOP
TLBR
NOOP
MOVW M(TLBVIRT), R1
MOVW M(TLBPHYS), R2
NOOP
MOVW R1, 0(R4)
MOVW R2, 4(R4)
RET
TEXT gettlbvirt(SB), $0
MOVW 0(FP), R3
SLL $8, R3
MOVW R3, M(INDEX)
NOOP
TLBR
NOOP
MOVW M(TLBVIRT), R1
NOOP
RET
TEXT vector80(SB), $-4
MOVW $exception(SB), R26
JMP (R26)
TEXT exception(SB), $-4
MOVW M(STATUS), R26
AND $KUP, R26
BEQ R26, waskernel
wasuser:
MOVW SP, R26
/*
* set kernel sp: ureg - ureg* - pc
* done in 2 steps because R30 is not set
* and the loader will make a literal
*/
MOVW $((UREGADDR-2*BY2WD) & 0xffff0000), SP
OR $((UREGADDR-2*BY2WD) & 0xffff), SP
MOVW R26, 0x10(SP) /* user SP */
MOVW R31, 0x28(SP)
MOVW R30, 0x2C(SP)
MOVW M(CAUSE), R26
MOVW R(MACH), 0x3C(SP)
MOVW R(USER), 0x40(SP)
AND $(0xF<<2), R26
SUB $(CSYS<<2), R26
JAL saveregs(SB)
MOVW $setR30(SB), R30
SUBU $(UREGADDR-2*BY2WD-USERADDR), SP, R(USER)
MOVW $MPID, R1
MOVB 3(R1), R1
MOVW $MACHADDR, R(MACH) /* locn of mach 0 */
AND $7, R1
SLL $PGSHIFT, R1
ADDU R1, R(MACH) /* add offset for mach # */
BNE R26, notsys
JAL syscall(SB)
MOVW 0x28(SP), R31
MOVW 0x08(SP), R26
MOVW 0x2C(SP), R30
MOVW R26, M(STATUS)
NOOP
MOVW 0x0C(SP), R26 /* old pc */
MOVW 0x10(SP), SP
RFE (R26)
notsys:
JAL trap(SB)
restore:
JAL restregs(SB)
MOVW 0x28(SP), R31
MOVW 0x2C(SP), R30
MOVW 0x3C(SP), R(MACH)
MOVW 0x40(SP), R(USER)
MOVW 0x10(SP), SP
RFE (R26)
waskernel:
MOVW $1, R26 /* not sys call */
MOVW SP, -0x90(SP) /* drop this if possible */
SUB $0xA0, SP
MOVW R31, 0x28(SP)
JAL saveregs(SB)
JAL trap(SB)
JAL restregs(SB)
MOVW 0x28(SP), R31
ADD $0xA0, SP
RFE (R26)
TEXT saveregs(SB), $-4
MOVW R1, 0x9C(SP)
MOVW R2, 0x98(SP)
ADDU $8, SP, R1
MOVW R1, 0x04(SP) /* arg to base of regs */
MOVW M(STATUS), R1
MOVW M(EPC), R2
MOVW R1, 0x08(SP)
MOVW R2, 0x0C(SP)
BEQ R26, return /* sys call, don't save */
MOVW M(CAUSE), R1
MOVW M(BADVADDR), R2
MOVW R1, 0x14(SP)
MOVW M(TLBVIRT), R1
MOVW R2, 0x18(SP)
MOVW R1, 0x1C(SP)
MOVW HI, R1
MOVW LO, R2
MOVW R1, 0x20(SP)
MOVW R2, 0x24(SP)
/* LINK,SB,SP missing */
MOVW R28, 0x30(SP)
/* R27, R26 not saved */
/* R25, R24 missing */
MOVW R23, 0x44(SP)
MOVW R22, 0x48(SP)
MOVW R21, 0x4C(SP)
MOVW R20, 0x50(SP)
MOVW R19, 0x54(SP)
MOVW R18, 0x58(SP)
MOVW R17, 0x5C(SP)
MOVW R16, 0x60(SP)
MOVW R15, 0x64(SP)
MOVW R14, 0x68(SP)
MOVW R13, 0x6C(SP)
MOVW R12, 0x70(SP)
MOVW R11, 0x74(SP)
MOVW R10, 0x78(SP)
MOVW R9, 0x7C(SP)
MOVW R8, 0x80(SP)
MOVW R7, 0x84(SP)
MOVW R6, 0x88(SP)
MOVW R5, 0x8C(SP)
MOVW R4, 0x90(SP)
MOVW R3, 0x94(SP)
return:
RET
TEXT restregs(SB), $-4
/* LINK,SB,SP missing */
MOVW 0x30(SP), R28
/* R27, R26 not saved */
/* R25, R24 missing */
MOVW 0x44(SP), R23
MOVW 0x48(SP), R22
MOVW 0x4C(SP), R21
MOVW 0x50(SP), R20
MOVW 0x54(SP), R19
MOVW 0x58(SP), R18
MOVW 0x5C(SP), R17
MOVW 0x60(SP), R16
MOVW 0x64(SP), R15
MOVW 0x68(SP), R14
MOVW 0x6C(SP), R13
MOVW 0x70(SP), R12
MOVW 0x74(SP), R11
MOVW 0x78(SP), R10
MOVW 0x7C(SP), R9
MOVW 0x80(SP), R8
MOVW 0x84(SP), R7
MOVW 0x88(SP), R6
MOVW 0x8C(SP), R5
MOVW 0x90(SP), R4
MOVW 0x94(SP), R3
MOVW 0x24(SP), R2
MOVW 0x20(SP), R1
MOVW R2, LO
MOVW R1, HI
MOVW 0x08(SP), R1
MOVW 0x98(SP), R2
MOVW R1, M(STATUS)
NOOP
MOVW 0x9C(SP), R1
MOVW 0x0C(SP), R26 /* old pc */
RET
TEXT rfnote(SB), $0
MOVW 0(FP), R26 /* 1st arg is &uregpointer */
SUBU $(BY2WD), R26, SP /* pc hole */
BNE R26, restore
TEXT clrfpintr(SB), $0
MOVW FCR31, R1
MOVW R1, R2
AND $~(0x3F<<12), R2
MOVW R2, FCR31
RET
TEXT savefpregs(SB), $0
MOVW M(STATUS), R3
MOVW 0(FP), R1
MOVW FCR31, R2
MOVD F0, 0x00(R1)
MOVD F2, 0x08(R1)
MOVD F4, 0x10(R1)
MOVD F6, 0x18(R1)
MOVD F8, 0x20(R1)
MOVD F10, 0x28(R1)
MOVD F12, 0x30(R1)
MOVD F14, 0x38(R1)
MOVD F16, 0x40(R1)
MOVD F18, 0x48(R1)
MOVD F20, 0x50(R1)
MOVD F22, 0x58(R1)
MOVD F24, 0x60(R1)
MOVD F26, 0x68(R1)
MOVD F28, 0x70(R1)
MOVD F30, 0x78(R1)
MOVW R2, 0x80(R1)
AND $~CU1, R3
MOVW R3, M(STATUS)
RET
TEXT restfpregs(SB), $0
MOVW M(STATUS), R3
MOVW 0(FP), R1
OR $CU1, R3
MOVW R3, M(STATUS)
MOVW 0x80(R1), R2
MOVD 0x00(R1), F0
MOVD 0x08(R1), F2
MOVD 0x10(R1), F4
MOVD 0x18(R1), F6
MOVD 0x20(R1), F8
MOVD 0x28(R1), F10
MOVD 0x30(R1), F12
MOVD 0x38(R1), F14
MOVD 0x40(R1), F16
MOVD 0x48(R1), F18
MOVD 0x50(R1), F20
MOVD 0x58(R1), F22
MOVD 0x60(R1), F24
MOVD 0x68(R1), F26
MOVD 0x70(R1), F28
MOVD 0x78(R1), F30
MOVW R2, FCR31
AND $~CU1, R3
MOVW R3, M(STATUS)
RET
/*
* we avoid using R4, R5, R6, and R7 so gotopc can call us without saving them
*/
TEXT icflush(SB), $-4 /* icflush(physaddr, nbytes) */
MOVW M(STATUS), R10
MOVW 0(FP), R8
MOVW 4(FP), R9
MOVW $KSEG0, R3
OR R3, R8
MOVW $0, M(STATUS)
MOVW $WBFLUSH, R1 /* wbflush */
MOVW 0(R1), R1
NOOP
MOVW $KSEG1, R3
MOVW $icflush0(SB), R2 /* make sure PC is in uncached address space */
MOVW $(SWC|ISC), R1
OR R3, R2
JMP (R2)
TEXT icflush0(SB), $-4
MOVW R1, M(STATUS) /* swap and isolate cache, splhi */
MOVW $icflush1(SB), R2
JMP (R2)
TEXT icflush1(SB), $-4
_icflush1:
MOVBU R0, 0x00(R8)
MOVBU R0, 0x04(R8)
MOVBU R0, 0x08(R8)
MOVBU R0, 0x0C(R8)
MOVBU R0, 0x10(R8)
MOVBU R0, 0x14(R8)
MOVBU R0, 0x18(R8)
MOVBU R0, 0x1C(R8)
MOVBU R0, 0x20(R8)
MOVBU R0, 0x24(R8)
MOVBU R0, 0x28(R8)
MOVBU R0, 0x2C(R8)
MOVBU R0, 0x30(R8)
MOVBU R0, 0x34(R8)
MOVBU R0, 0x38(R8)
MOVBU R0, 0x3C(R8)
SUB $0x40, R9
ADD $0x40, R8
BGTZ R9, _icflush1
MOVW $icflush2(SB), R2 /* make sure PC is in uncached address space */
OR R3, R2
JMP (R2)
TEXT icflush2(SB), $-4
MOVW $0, M(STATUS) /* swap back caches, de-isolate them, and stay splhi */
NOOP /* +++ */
MOVW R10, M(STATUS)
RET
TEXT dcflush(SB), $-4 /* dcflush(physaddr, nbytes) */
MOVW M(STATUS), R6
MOVW 0(FP), R4
MOVW 4(FP), R5
MOVW $KSEG0, R3
OR R3, R4
MOVW $0, M(STATUS)
MOVW $WBFLUSH, R1
MOVW 0(R1), R1
NOOP
MOVW $ISC, R1
MOVW R1, M(STATUS)
_dcflush0:
MOVBU R0, 0x00(R4)
MOVBU R0, 0x04(R4)
MOVBU R0, 0x08(R4)
MOVBU R0, 0x0C(R4)
MOVBU R0, 0x10(R4)
MOVBU R0, 0x14(R4)
MOVBU R0, 0x18(R4)
MOVBU R0, 0x1C(R4)
MOVBU R0, 0x20(R4)
MOVBU R0, 0x24(R4)
MOVBU R0, 0x28(R4)
MOVBU R0, 0x2C(R4)
MOVBU R0, 0x30(R4)
MOVBU R0, 0x34(R4)
MOVBU R0, 0x38(R4)
MOVBU R0, 0x3C(R4)
SUB $0x40, R5
ADD $0x40, R4
BGTZ R5, _dcflush0
MOVW $0, M(STATUS)
NOOP /* +++ */
MOVW R6, M(STATUS)
RET