nusb/ether: add support for lan78xx (raspi3) (thanks richard miller)
This commit is contained in:
cinap_lenrek
parent
29865005f9
commit
86a9f92f47
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@ -886,6 +886,7 @@ extern int aueinit(Dev *);
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extern int a88178init(Dev *);
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extern int a88772init(Dev *);
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extern int smscinit(Dev *);
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extern int lan78xxinit(Dev *);
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extern int cdcinit(Dev *);
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extern int urlinit(Dev *);
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extern int rndisinit(Dev *);
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@ -896,6 +897,7 @@ static struct {
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} ethertype[] = {
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"cdc", cdcinit,
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"smsc", smscinit,
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"lan78xx", lan78xxinit,
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"a88178", a88178init,
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"a88772", a88772init,
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"aue", aueinit,
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@ -921,7 +923,8 @@ threadmain(int argc, char **argv)
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break;
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case 'a':
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setmac = 1;
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parseether(macaddr, EARGF(usage()));
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if(parseether(macaddr, EARGF(usage())) != 0)
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usage();
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break;
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case 't':
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t = EARGF(usage());
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366
sys/src/cmd/nusb/ether/lan78xx.c
Normal file
366
sys/src/cmd/nusb/ether/lan78xx.c
Normal file
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@ -0,0 +1,366 @@
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/*
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* Microchip (ex SMSC) LAN78XX
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* Also used as ethernet core in LAN7515 usb hub + ethernet
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*/
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#include <u.h>
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#include <libc.h>
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#include <thread.h>
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#include "usb.h"
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#include "dat.h"
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enum {
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Doburst = 1,
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Resettime = 1000,
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E2pbusytime = 1000,
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Hsburst = 32,
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Defbulkdly = 1000,
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Rxfifosize = (12*1024),
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Txfifosize = (12*1024),
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MACoffset = 1,
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PHYinternal = 1,
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Rxerror = 0x00400000,
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Txfcs = 1<<22,
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/* USB vendor requests */
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Writereg = 0xA0,
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Readreg = 0xA1,
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/* device registers */
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Idrev = 0x00,
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Intsts = 0x0C,
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Hwcfg = 0x10,
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Led0en = 1<<20,
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Led1en = 1<<21,
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Mef = 1<<4,
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Lrst = 1<<1,
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Pmctrl = 0x14,
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Ready = 1<<7,
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Phyrst = 1<<4,
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Gpiocfg0 = 0x18,
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Gpiocfg1 = 0x1C,
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E2pcmd = 0x40,
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Busy = 1<<31,
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Timeout = 1<<10,
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Loaded = 1<<9,
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Read = 0,
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E2pdata = 0x44,
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Burstcap = 0x90,
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Intepctl = 0x98,
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Phyint = 1<<17,
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Bulkdelay = 0x94,
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Rfectl = 0xB0,
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Rxcoe = 0xF<<11,
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Ab = 1<<10,
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Am = 1<<9,
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Au = 1<<8,
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Dpf = 1<<1,
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Usbcfg0 = 0x80,
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Bir = 1<<6,
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Bce = 1<<5,
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Usbcfg1 = 0x84,
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Rxfifoctl = 0xC0,
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Rxen = 1<<31,
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Txfifoctl = 0xC4,
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Txen = 1<<31,
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Rxfifo = 0xC8,
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Txfifo = 0xCc,
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Fctflow = 0xD0,
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Maccr = 0x100,
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Add = 1<<12,
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Asd = 1<<11,
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Macrx = 0x104,
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Macfcs = 1<<4,
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Macrxen = 1<<0,
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Mactx = 0x108,
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Mactxen = 1<<0,
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Addrh = 0x118,
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Addrl = 0x11C,
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MIIaddr = 0x120,
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MIIwrite= 1<<1,
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MIIread = 0<<1,
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MIIbusy = 1<<0,
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MIIdata = 0x124,
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Flow = 0x10C,
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Addrfilth = 0x400,
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Afvalid = 1<<31,
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Addrfiltl = 0x404,
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/* MII registers */
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Bmcr = 0,
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Bmcrreset= 1<<15,
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Speed100= 1<<13,
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Anenable= 1<<12,
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Anrestart= 1<<9,
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Fulldpx = 1<<8,
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Speed1000= 1<<6,
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Bmsr = 1,
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Advertise = 4,
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Adcsma = 0x0001,
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Ad10h = 0x0020,
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Ad10f = 0x0040,
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Ad100h = 0x0080,
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Ad100f = 0x0100,
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Adpause = 0x0400,
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Adpauseasym= 0x0800,
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Adall = Ad10h|Ad10f|Ad100h|Ad100f,
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Lpa = 5,
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Ctrl1000 = 9,
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Ad1000h = 0x0400,
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Ad1000f = 0x0200,
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Ledmodes = 29,
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Led0shift = 0,
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Led1shift = 4,
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Linkact = 0x0,
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Link1000 = 0x1,
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Phyintmask = 25,
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Anegcomp= 1<<10,
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Linkchg = 1<<13,
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};
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static int burstcap = Hsburst, bulkdelay = Defbulkdly;
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static int
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wr(Dev *d, int reg, int val)
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{
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int ret;
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ret = usbcmd(d, Rh2d|Rvendor|Rdev, Writereg, 0, reg,
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(uchar*)&val, sizeof(val));
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if(ret < 0)
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fprint(2, "%s: wr(%x, %x): %r", argv0, reg, val);
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return ret;
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}
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static int
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rr(Dev *d, int reg)
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{
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int ret, rval;
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ret = usbcmd(d, Rd2h|Rvendor|Rdev, Readreg, 0, reg,
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(uchar*)&rval, sizeof(rval));
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if(ret < 0){
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fprint(2, "%s: rr(%x): %r", argv0, reg);
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return 0;
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}
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return rval;
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}
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static int
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miird(Dev *d, int idx)
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{
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while(rr(d, MIIaddr) & MIIbusy)
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;
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wr(d, MIIaddr, PHYinternal<<11 | idx<<6 | MIIread | MIIbusy);
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while(rr(d, MIIaddr) & MIIbusy)
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;
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return rr(d, MIIdata);
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}
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static void
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miiwr(Dev *d, int idx, int val)
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{
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while(rr(d, MIIaddr) & MIIbusy)
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;
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wr(d, MIIdata, val);
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wr(d, MIIaddr, PHYinternal<<11 | idx<<6 | MIIwrite | MIIbusy);
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while(rr(d, MIIaddr) & MIIbusy)
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;
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}
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static int
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eepromr(Dev *d, int off, uchar *buf, int len)
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{
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int i, v;
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for(i = 0; i < E2pbusytime; i++)
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if((rr(d, E2pcmd) & Busy) == 0)
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break;
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if(i == E2pbusytime)
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return -1;
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for(i = 0; i < len; i++){
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wr(d, E2pcmd, Busy|Read|(i+off));
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while((v = rr(d, E2pcmd) & (Busy|Timeout)) == Busy)
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;
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if(v & Timeout)
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return -1;
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buf[i] = rr(d, E2pdata);
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}
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return 0;
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}
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static void
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phyinit(Dev *d)
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{
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int i;
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miiwr(d, Bmcr, Bmcrreset|Anenable);
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for(i = 0; i < Resettime/10; i++){
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if((miird(d, Bmcr) & Bmcrreset) == 0)
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break;
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sleep(10);
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}
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miiwr(d, Advertise, Adcsma|Adall|Adpause|Adpauseasym);
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miiwr(d, Ctrl1000, Ad1000f);
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miiwr(d, Phyintmask, 0);
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miiwr(d, Ledmodes, (Linkact<<Led1shift) | (Link1000<<Led0shift));
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miiwr(d, Bmcr, miird(d, Bmcr)|Anenable|Anrestart);
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}
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static int
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doreset(Dev *d, int reg, int bit)
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{
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int i;
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if(wr(d, reg, bit) < 0)
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return -1;
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for(i = 0; i < Resettime/10; i++){
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if((rr(d, reg) & bit) == 0)
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return 1;
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sleep(10);
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}
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return 0;
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}
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static int
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lan78xxreceive(Dev *ep)
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{
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Block *b;
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uint hd;
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int n;
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n = Doburst? burstcap*512: Maxpkt;
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b = allocb(n);
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if((n = read(ep->dfd, b->wp, n)) < 10){
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freeb(b);
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return -1;
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}
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b->wp += n;
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while(BLEN(b) >= 10){
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hd = GET4(b->rp);
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b->rp += 10;
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n = hd & 0x3FFF;
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if(n > BLEN(b))
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break;
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if((hd & Rxerror) == 0){
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if(n == BLEN(b)){
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etheriq(b);
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return 0;
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}
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etheriq(copyblock(b, n));
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}
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b->rp = (uchar*)(((uintptr)b->rp + n + 3)&~3);
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}
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freeb(b);
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return 0;
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}
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static void
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lan78xxtransmit(Dev *ep, Block *b)
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{
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int n = BLEN(b) & 0xFFFFF;
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b->rp -= 8;
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PUT4(b->rp, n | Txfcs);
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PUT4(b->rp+4, n);
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write(ep->dfd, b->rp, BLEN(b));
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freeb(b);
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}
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static int
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lan78xxpromiscuous(Dev *d, int on)
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{
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int rxctl;
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rxctl = rr(d, Rfectl);
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if(on)
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rxctl |= Am|Au;
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else {
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rxctl &= ~Au;
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if(nmulti == 0)
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rxctl &= ~Am;
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}
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return wr(d, Rfectl, rxctl);
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}
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static int
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lan78xxmulticast(Dev *d, uchar *, int)
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{
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int rxctl;
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rxctl = rr(d, Rfectl);
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if(nmulti != 0)
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rxctl |= Am;
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else
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rxctl &= ~Am;
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return wr(d, Rfectl, rxctl);
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}
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int
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lan78xxinit(Dev *d)
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{
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u32int a;
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int i;
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if(!doreset(d, Hwcfg, Lrst) || !doreset(d, Pmctrl, Phyrst))
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return -1;
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for(i = 0; i < Resettime/10; i++){
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if(rr(d, Pmctrl) & Ready)
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break;
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sleep(10);
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}
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if((rr(d, Pmctrl) & Ready) == 0){
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fprint(2, "%s: device not ready after reset\n", argv0);
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return -1;
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}
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if(!setmac)
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if(eepromr(d, MACoffset, macaddr, Eaddrlen) < 0)
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fprint(2, "%s: can't read etheraddr from EEPROM\n", argv0);
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a = GET4(macaddr);
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wr(d, Addrl, a);
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wr(d, Addrfiltl, a);
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a = GET2(macaddr+4);
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wr(d, Addrh, a);
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wr(d, Addrfilth, a|Afvalid);
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wr(d, Usbcfg0, rr(d, Usbcfg0) | Bir);
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if(Doburst){
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wr(d, Hwcfg, rr(d, Hwcfg)|Mef);
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wr(d, Usbcfg0, rr(d, Usbcfg0)|Bce);
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wr(d, Burstcap, burstcap);
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wr(d, Bulkdelay, bulkdelay);
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}else{
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wr(d, Hwcfg, rr(d, Hwcfg)&~Mef);
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wr(d, Usbcfg0, rr(d, Usbcfg0)&~Bce);
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wr(d, Burstcap, 0);
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wr(d, Bulkdelay, 0);
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}
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wr(d, Rxfifo, (Rxfifosize-512)/512);
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wr(d, Txfifo, (Txfifosize-512)/512);
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wr(d, Intsts, ~0);
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wr(d, Hwcfg, rr(d, Hwcfg) | Led0en|Led1en);
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wr(d, Flow, 0);
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wr(d, Fctflow, 0);
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wr(d, Rfectl, (rr(d, Rfectl) & ~Rxcoe) | Ab|Dpf); /* TODO could offload checksums? */
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phyinit(d);
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wr(d, Maccr, rr(d,Maccr)|Add|Asd);
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wr(d, Intepctl, rr(d, Intepctl)|Phyint);
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wr(d, Mactx, Mactxen);
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wr(d, Macrx, rr(d, Macrx) | Macfcs|Macrxen);
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wr(d, Txfifoctl, Txen);
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wr(d, Rxfifoctl, Rxen);
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eptransmit = lan78xxtransmit;
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epreceive = lan78xxreceive;
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eppromiscuous = lan78xxpromiscuous;
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epmulticast = lan78xxmulticast;
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return 0;
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}
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@ -5,7 +5,7 @@ LIB=../lib/usb.a$O
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TARG=ether
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HFILES=../lib/usb.h dat.h
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OFILES=ether.$O cdc.$O smsc.$O asix.$O aue.$O url.$O rndis.$O
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OFILES=ether.$O cdc.$O smsc.$O lan78xx.$O asix.$O aue.$O url.$O rndis.$O
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</sys/src/cmd/mkone
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