pckernel: use constants instead of hardcoding cpuid bits in various places
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81954dbf25
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7fdf820589
7 changed files with 12 additions and 11 deletions
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@ -283,7 +283,8 @@ enum {
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/* dx */
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/* dx */
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Fpuonchip = 1<<0,
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Fpuonchip = 1<<0,
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// Pse = 1<<3, /* page size extensions */
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Vmex = 1<<1, /* virtual-mode extensions */
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Pse = 1<<3, /* page size extensions */
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Tsc = 1<<4, /* time-stamp counter */
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Tsc = 1<<4, /* time-stamp counter */
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Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
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Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
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Pae = 1<<6, /* physical-addr extensions */
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Pae = 1<<6, /* physical-addr extensions */
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@ -292,7 +293,7 @@ enum {
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Cpuapic = 1<<9,
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Cpuapic = 1<<9,
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Mtrr = 1<<12, /* memory-type range regs. */
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Mtrr = 1<<12, /* memory-type range regs. */
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Pge = 1<<13, /* page global extension */
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Pge = 1<<13, /* page global extension */
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// Pse2 = 1<<17, /* more page size extensions */
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Pse2 = 1<<17, /* more page size extensions */
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Clflush = 1<<19,
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Clflush = 1<<19,
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Acpif = 1<<22, /* therm control msr */
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Acpif = 1<<22, /* therm control msr */
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Mmx = 1<<23,
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Mmx = 1<<23,
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@ -809,9 +809,9 @@ cpuidentify(void)
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* are supported enable them in CR4 and clear any other set extensions.
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* are supported enable them in CR4 and clear any other set extensions.
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* If machine check was enabled clear out any lingering status.
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* If machine check was enabled clear out any lingering status.
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*/
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*/
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if(m->cpuiddx & (Pge|Mce|0x8)){
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if(m->cpuiddx & (Pge|Mce|Pse)){
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cr4 = 0;
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cr4 = 0;
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if(m->cpuiddx & 0x08)
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if(m->cpuiddx & Pse)
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cr4 |= 0x10; /* page size extensions */
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cr4 |= 0x10; /* page size extensions */
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if(p = getconf("*nomce"))
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if(p = getconf("*nomce"))
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nomce = strtoul(p, 0, 0);
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nomce = strtoul(p, 0, 0);
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@ -523,7 +523,7 @@ matherror(Ureg *ur, void*)
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* a write cycle to port 0xF0 clears the interrupt latch attached
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* a write cycle to port 0xF0 clears the interrupt latch attached
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* to the error# line from the 387
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* to the error# line from the 387
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*/
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*/
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if(!(m->cpuiddx & 0x01))
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if(!(m->cpuiddx & Fpuonchip))
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outb(0xF0, 0xFF);
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outb(0xF0, 0xFF);
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/*
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/*
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@ -473,9 +473,9 @@ ramscan(ulong maxmem)
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table = &m->pdb[PDX(KADDR(pa - 4*MB))];
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table = &m->pdb[PDX(KADDR(pa - 4*MB))];
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if(nvalid[MemUPA] == (4*MB)/BY2PG)
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if(nvalid[MemUPA] == (4*MB)/BY2PG)
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*table = 0;
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*table = 0;
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else if(nvalid[MemRAM] == (4*MB)/BY2PG && (m->cpuiddx & 0x08))
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else if(nvalid[MemRAM] == (4*MB)/BY2PG && (m->cpuiddx & Pse))
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*table = (pa - 4*MB)|PTESIZE|PTEWRITE|PTEVALID;
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*table = (pa - 4*MB)|PTESIZE|PTEWRITE|PTEVALID;
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else if(nvalid[MemUMB] == (4*MB)/BY2PG && (m->cpuiddx & 0x08))
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else if(nvalid[MemUMB] == (4*MB)/BY2PG && (m->cpuiddx & Pse))
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*table = (pa - 4*MB)|PTESIZE|PTEWRITE|PTEUNCACHED|PTEVALID;
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*table = (pa - 4*MB)|PTESIZE|PTEWRITE|PTEUNCACHED|PTEVALID;
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else{
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else{
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*table = map|PTEWRITE|PTEVALID;
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*table = map|PTEWRITE|PTEVALID;
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@ -712,7 +712,7 @@ pdbmap(ulong *pdb, ulong pa, ulong va, int size)
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flag = pa&0xFFF;
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flag = pa&0xFFF;
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pa &= ~0xFFF;
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pa &= ~0xFFF;
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if((MACHP(0)->cpuiddx & 0x08) && (getcr4() & 0x10))
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if((MACHP(0)->cpuiddx & Pse) && (getcr4() & 0x10))
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pse = 1;
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pse = 1;
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else
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else
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pse = 0;
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pse = 0;
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@ -99,7 +99,7 @@ checkmtrr(void)
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/*
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/*
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* If there are MTRR registers, snarf them for validation.
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* If there are MTRR registers, snarf them for validation.
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*/
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*/
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if(!(m->cpuiddx & 0x1000))
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if(!(m->cpuiddx & Mtrr))
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return;
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return;
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rdmsr(0x0FE, &m->mtrrcap);
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rdmsr(0x0FE, &m->mtrrcap);
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@ -535,9 +535,9 @@ dumpregs(Ureg* ureg)
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*/
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*/
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iprint(" CR0 %8.8lux CR2 %8.8lux CR3 %8.8lux",
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iprint(" CR0 %8.8lux CR2 %8.8lux CR3 %8.8lux",
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getcr0(), getcr2(), getcr3());
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getcr0(), getcr2(), getcr3());
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if(m->cpuiddx & 0x9A){
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if(m->cpuiddx & (Mce|Tsc|Pse|Vmex)){
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iprint(" CR4 %8.8lux", getcr4());
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iprint(" CR4 %8.8lux", getcr4());
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if((m->cpuiddx & 0xA0) == 0xA0){
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if((m->cpuiddx & (Mce|Cpumsr)) == (Mce|Cpumsr)){
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rdmsr(0x00, &mca);
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rdmsr(0x00, &mca);
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rdmsr(0x01, &mct);
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rdmsr(0x01, &mct);
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iprint("\n MCA %8.8llux MCT %8.8llux", mca, mct);
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iprint("\n MCA %8.8llux MCT %8.8llux", mca, mct);
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