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igfx: fix FDI link training on ironlake

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Ironlake uses bits 29:28 in the RX control register to select the
training pattern.
This commit is contained in:
Michael Forney 2022-03-02 10:26:38 +00:00 committed by cinap_lenrek
parent 9c02337fc3
commit 79c7e4514d
1 changed files with 19 additions and 8 deletions
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21
sys/src/cmd/aux/vga/igfx.c
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@ -1465,12 +1465,17 @@ enablepipe(Igfx *igfx, int x)
/* unmask bit lock and symbol lock bits */
csr(igfx, p->fdi->rximr.a, 3<<8, 0);
p->fdi->txctl.v &= ~(3<<28); /* link train pattern1 */
p->fdi->txctl.v |= 1<<31; /* enable */
loadreg(igfx, p->fdi->txctl);
/* enable fdi */
p->fdi->txctl.v |= 1<<31;
p->fdi->rxctl.v |= 1<<31;
p->fdi->rxctl.v &= ~(3<<8); /* link train pattern1 */
p->fdi->rxctl.v |= 1<<31; /* enable */
/* switch to link train pattern1 */
p->fdi->txctl.v &= ~(3<<28);
loadreg(igfx, p->fdi->txctl);
if(igfx->type == TypeILK)
p->fdi->rxctl.v &= ~(3<<28);
else
p->fdi->rxctl.v &= ~(3<<8);
loadreg(igfx, p->fdi->rxctl);
/* wait for bit lock */
@ -1483,6 +1488,9 @@ enablepipe(Igfx *igfx, int x)
/* switch to link train pattern2 */
csr(igfx, p->fdi->txctl.a, 3<<28, 1<<28);
if(igfx->type == TypeILK)
csr(igfx, p->fdi->rxctl.a, 3<<28, 1<<28);
else
csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
/* wait for symbol lock */
@ -1495,6 +1503,9 @@ enablepipe(Igfx *igfx, int x)
/* switch to link train normal */
csr(igfx, p->fdi->txctl.a, 0, 3<<28);
if(igfx->type == TypeILK)
csr(igfx, p->fdi->rxctl.a, 0, 3<<28);
else
csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
/* wait idle pattern time */