games/gba: small fixes

This commit is contained in:
aiju 2014-09-28 19:41:52 +02:00
parent 15afb9d00b
commit 752841fcc1
3 changed files with 16 additions and 17 deletions

View file

@ -238,7 +238,7 @@ armextra(u32int instr)
addr = r[Rn]; addr = r[Rn];
if((instr & 0x0ffffff0) == 0x012fff10){ if((instr & 0x0ffffff0) == 0x012fff10){
r[14] = r[15] - 4; r[14] = r[15] - 4;
r[15] = r[Rm]; r[15] = r[Rm] & ~1;
setcpsr(cpsr | FLAGT); setcpsr(cpsr | FLAGT);
pipeflush(); pipeflush();
}else if((instr & BYTE) != 0){ }else if((instr & BYTE) != 0){
@ -253,7 +253,7 @@ armextra(u32int instr)
sh = (addr & 3) << 2; sh = (addr & 3) << 2;
val = val >> sh | val << 32 - sh; val = val >> sh | val << 32 - sh;
} }
memwrite(addr, r[Rm], 4); memwrite(addr & ~3, r[Rm], 4);
r[Rd] = val; r[Rd] = val;
} }
}else{ }else{
@ -935,7 +935,7 @@ thalu(u16int instr)
if(b != 0){ if(b != 0){
if(b < 32){ if(b < 32){
c = v >> b - 1; c = v >> b - 1;
v >>= b; v = (int)v >> b;
}else }else
c = v = -((int)v < 0); c = v = -((int)v < 0);
cpsr = cpsr & ~FLAGC | c << 29 & FLAGC; cpsr = cpsr & ~FLAGC | c << 29 & FLAGC;
@ -1084,7 +1084,7 @@ thldst(u16int instr)
off += r[Rb]; off += r[Rb];
if(load){ if(load){
io(); io();
v = memread(off & ~(size - 1), size, 0); v = memread(off & -size, size, 0);
if(sx) if(sx)
if(size == 2) if(size == 2)
v = ((int)(v << 16)) >> 16; v = ((int)(v << 16)) >> 16;
@ -1096,7 +1096,7 @@ thldst(u16int instr)
} }
r[Rd] = v; r[Rd] = v;
}else }else
memwrite(off, r[Rd], size); memwrite(off & -size, r[Rd], size);
} }
static void static void

View file

@ -283,6 +283,7 @@ keyproc(void *)
break; break;
} }
} }
k &= ~(k << 1 & 0xa0 | k >> 1 & 0x50);
keys = k; keys = k;
} }

View file

@ -128,6 +128,10 @@ regwrite16(u32int a, u16int v)
*p &= ~v; *p &= ~v;
setif(0); setif(0);
return; return;
case IME*2: case IE*2:
*p = v;
setif(0);
return;
case BLDALPHA*2: case BLDALPHA*2:
blda = v & 0x1f; blda = v & 0x1f;
if(blda > 16) if(blda > 16)
@ -142,8 +146,8 @@ regwrite16(u32int a, u16int v)
bldy = 16; bldy = 16;
break; break;
case DMA0CNTH*2: case DMA1CNTH*2: case DMA2CNTH*2: case DMA3CNTH*2: case DMA0CNTH*2: case DMA1CNTH*2: case DMA2CNTH*2: case DMA3CNTH*2:
if((*p & DMAEN) == 0 && (v & DMAEN) != 0){
i = (a - DMA0CNTH*2) / 12; i = (a - DMA0CNTH*2) / 12;
if((v & DMAEN) != 0){
if((v >> DMAWHEN & 3) == 0) if((v >> DMAWHEN & 3) == 0)
dmaact |= 1<<i; dmaact |= 1<<i;
if(i == 3 && (v >> DMAWHEN & 3) == 3) if(i == 3 && (v >> DMAWHEN & 3) == 3)
@ -151,15 +155,13 @@ regwrite16(u32int a, u16int v)
dmar[4*i + DMASRC] = p[-5] | p[-4] << 16; dmar[4*i + DMASRC] = p[-5] | p[-4] << 16;
dmar[4*i + DMADST] = p[-3] | p[-2] << 16; dmar[4*i + DMADST] = p[-3] | p[-2] << 16;
dmar[4*i + DMACNT] = p[-1]; dmar[4*i + DMACNT] = p[-1];
} }else
dmaact &= ~1<<i;
break; break;
case 0x102: case 0x106: case 0x10a: case 0x10e: case 0x102: case 0x106: case 0x10a: case 0x10e:
if((*p & 1<<7) == 0 && (v & 1<<7) != 0) if((*p & 1<<7) == 0 && (v & 1<<7) != 0)
tim[(a-0x102)/4] = p[-1]; tim[(a-0x102)/4] = p[-1];
break; break;
case IME*2: case IE*2:
setif(0);
break;
case WAITCNT*2: case WAITCNT*2:
waitst[3] = waitst[7] = ws0[v & 3]; waitst[3] = waitst[7] = ws0[v & 3];
waitst[0] = ws0[v >> 2 & 3]; waitst[0] = ws0[v >> 2 & 3];
@ -196,13 +198,9 @@ regwrite(u32int a, u32int v, int n)
regwrite16(a, w); regwrite16(a, w);
break; break;
default: default:
if((a & 1) != 0)
sysfatal("unaligned register access");
regwrite16(a, v); regwrite16(a, v);
break; break;
case 4: case 4:
if((a & 1) != 0)
sysfatal("unaligned register access");
regwrite16(a, v); regwrite16(a, v);
regwrite16(a + 2, v >> 16); regwrite16(a + 2, v >> 16);
break; break;
@ -277,7 +275,7 @@ memread(u32int a, int n, int seq)
return 0; return 0;
default: default:
fault: fault:
sysfatal("read from %#.8ux (pc=%#.8ux)", a, curpc); print("read from %#.8ux (pc=%#.8ux)\n", a, curpc);
return 0; return 0;
} }
} }
@ -346,7 +344,7 @@ memwrite(u32int a, u32int v, int n)
return; return;
default: default:
fault: fault:
sysfatal("write to %#.8ux, value %#.8ux (pc=%#.8ux)", a, v, curpc); print("write to %#.8ux, value %#.8ux (pc=%#.8ux)\n", a, v, curpc);
} }
} }