imx8/usdhc: cleanup, set pad configuration
This commit is contained in:
cinap_lenrek
parent
15140dcce2
commit
63092af6a9
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@ -7,11 +7,6 @@
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#include "io.h"
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#include "../port/sd.h"
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#define USDHC1 (VIRTIO+0xB40000)
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#define USDHC2 (VIRTIO+0xB50000)
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#define EMMCREGS USDHC2
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enum {
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Initfreq = 400000, /* initialisation frequency for MMC */
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SDfreq = 25*Mhz, /* standard SD frequency */
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@ -21,10 +16,10 @@ enum {
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MMCSelect = 7, /* mmc/sd card select command */
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Setbuswidth = 6, /* mmc/sd set bus width command */
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Switchfunc = 6, /* mmc/sd switch function command */
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Voltageswitch = 11, /* md/sdio switch to 1.8V */
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IORWdirect = 52, /* sdio read/write direct command */
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IORWextended = 53, /* sdio read/write extended command */
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Appcmd = 55, /* mmc/sd application command prefix */
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Voltageswitch = 11, /* md/sdio switch to 1.8V */
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IORWdirect = 52, /* sdio read/write direct command */
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IORWextended = 53, /* sdio read/write extended command */
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Appcmd = 55, /* mmc/sd application command prefix */
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};
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enum {
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@ -69,11 +64,10 @@ enum {
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DmaSDMA = 0<<8,
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DmaADMA1 = 1<<8,
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DmaADMA2 = 2<<8,
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EMODE = 3<<4,
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BE = 0<<4,
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HBE = 1<<4,
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LE = 2<<4,
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DwidthMask = 3<<1,
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Dwidth8 = 2<<1,
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Dwidth4 = 1<<1,
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@ -157,7 +151,6 @@ static int cmdinfo[64] = {
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[8] Resp48 | Ixchken | Crcchken,
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[9] Resp136,
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[11] Resp48 | Ixchken | Crcchken,
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[12] Resp48busy | Ixchken | Crcchken,
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[13] Resp48 | Ixchken | Crcchken,
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[16] Resp48,
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[17] Resp48 | Isdata | Card2host | Ixchken | Crcchken,
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@ -177,7 +170,6 @@ typedef struct Ctlr Ctlr;
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* ADMA2 descriptor
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* See SD Host Controller Simplified Specification Version 2.00
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*/
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struct Adma {
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u32int desc;
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u32int addr;
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@ -204,18 +196,19 @@ struct Ctlr {
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Adma *dma;
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};
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static Ctlr emmc;
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static Ctlr usdhc;
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static void mmcinterrupt(Ureg*, void*);
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static void usdhcinterrupt(Ureg*, void*);
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static u32int *regs = (u32int*)(VIRTIO+0xB50000); /* USDHC2 */
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#define RR(reg) (regs[reg])
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static void
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WR(int reg, u32int val)
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{
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u32int *r = (u32int*)EMMCREGS;
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if(0)print("WR %2.2ux %ux\n", reg<<2, val);
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coherence();
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r[reg] = val;
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regs[reg] = val;
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}
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static Adma*
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@ -244,10 +237,9 @@ dmaalloc(void *addr, int len)
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}
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static void
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emmcclk(uint freq)
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usdhcclk(uint freq)
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{
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u32int *r = (u32int*)EMMCREGS;
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uint pre_div = 1, post_div = 1, clk = emmc.extclk;
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uint pre_div = 1, post_div = 1, clk = usdhc.extclk;
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while(clk / (pre_div * 16) > freq && pre_div < 256)
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pre_div <<= 1;
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@ -255,41 +247,48 @@ emmcclk(uint freq)
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while(clk / (pre_div * post_div) > freq && post_div < 16)
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post_div++;
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WR(Vendorspec, r[Vendorspec] & ~ClkEn);
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WR(Vendorspec, RR(Vendorspec) & ~ClkEn);
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WR(Control1, (pre_div>>1)<<SDCLKFSshift | (post_div-1)<<DVSshift | DTO<<Datatoshift);
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delay(10);
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WR(Vendorspec, r[Vendorspec] | ClkEn | PerEn);
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while((r[Status] & Clkstable) == 0)
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WR(Vendorspec, RR(Vendorspec) | ClkEn | PerEn);
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while((RR(Status) & Clkstable) == 0)
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;
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}
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static int
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datadone(void*)
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{
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int i;
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u32int *r = (u32int*)EMMCREGS;
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i = r[Interrupt];
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return i & (Datadone|Err);
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return RR(Interrupt) & (Datadone|Err);
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}
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static int
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emmcinit(void)
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usdhcinit(void)
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{
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u32int *r = (u32int*)EMMCREGS;
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iomuxpad("pad_sd2_clk", "usdhc2_clk", "~LVTTL ~HYS ~PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_cmd", "usdhc2_cmd", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data0", "usdhc2_data0", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data1", "usdhc2_data1", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data2", "usdhc2_data2", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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iomuxpad("pad_sd2_data3", "usdhc2_data3", "~LVTTL HYS PUE ~ODE SLOW 75_OHM");
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setclkgate("usdhc2.ipg_clk", 1);
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setclkgate("usdhc2.ipg_clk", 0);
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setclkgate("usdhc2.ipg_clk_perclk", 0);
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setclkrate("usdhc2.ipg_clk_perclk", "system_pll1_clk", 200*Mhz);
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setclkgate("usdhc2.ipg_clk_perclk", 1);
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emmc.extclk = getclkrate("usdhc2.ipg_clk_perclk");
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if(emmc.extclk <= 0){
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print("emmc: usdhc2.ipg_clk_perclk not enabled\n");
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setclkgate("usdhc2.ipg_clk", 1);
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usdhc.extclk = getclkrate("usdhc2.ipg_clk_perclk");
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if(usdhc.extclk <= 0){
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print("usdhc: usdhc2.ipg_clk_perclk not enabled\n");
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return -1;
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}
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if(0)print("emmc control %8.8ux %8.8ux %8.8ux\n",
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r[Control0], r[Control1], r[Control2]);
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if(0)print("usdhc control %8.8ux %8.8ux %8.8ux\n",
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RR(Control0), RR(Control1), RR(Control2));
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WR(Control1, Srsthc);
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delay(10);
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while(r[Control1] & Srsthc)
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while(RR(Control1) & Srsthc)
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;
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WR(Control1, Srstdata);
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delay(10);
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@ -298,34 +297,31 @@ emmcinit(void)
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}
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static int
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emmcinquiry(char *inquiry, int inqlen)
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usdhcinquiry(char *inquiry, int inqlen)
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{
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return snprint(inquiry, inqlen, "USDHC Host Controller");
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}
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static void
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emmcenable(void)
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usdhcenable(void)
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{
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u32int *r = (u32int*)EMMCREGS;
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WR(Control0, 0);
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delay(1);
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WR(Vendorspec, r[Vendorspec] & ~Vsel);
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WR(Vendorspec, RR(Vendorspec) & ~Vsel);
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WR(Control0, LE | Dwidth1 | DmaADMA2);
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WR(Control1, 0);
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delay(1);
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WR(Vendorspec, r[Vendorspec] | HclkEn | IpgEn);
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emmcclk(Initfreq);
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WR(Vendorspec, RR(Vendorspec) | HclkEn | IpgEn);
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usdhcclk(Initfreq);
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WR(Irpten, 0);
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WR(Irptmask, ~(Cardintr|Dmaintr));
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WR(Interrupt, ~0);
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intrenable(IRQusdhc2, mmcinterrupt, nil, BUSUNKNOWN, "usdhc2");
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intrenable(IRQusdhc2, usdhcinterrupt, nil, BUSUNKNOWN, "usdhc2");
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}
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static int
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emmccmd(u32int cmd, u32int arg, u32int *resp)
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usdhccmd(u32int cmd, u32int arg, u32int *resp)
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{
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u32int *r = (u32int*)EMMCREGS;
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u32int c;
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int i;
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ulong now;
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@ -339,7 +335,7 @@ emmccmd(u32int cmd, u32int arg, u32int *resp)
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/*
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* CMD6 may be Setbuswidth or Switchfunc depending on Appcmd prefix
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*/
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if(cmd == Switchfunc && !emmc.appcmd)
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if(cmd == Switchfunc && !usdhc.appcmd)
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c |= Isdata|Card2host;
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if(c & Isdata)
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c |= Dmaen;
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@ -348,57 +344,57 @@ emmccmd(u32int cmd, u32int arg, u32int *resp)
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c |= Host2card;
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else
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c |= Card2host;
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if((r[Blksizecnt]&0xFFFF0000) != 0x10000)
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if((RR(Blksizecnt)&0xFFFF0000) != 0x10000)
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c |= Multiblock | Blkcnten;
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}
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/*
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* GoIdle indicates new card insertion: reset bus width & speed
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*/
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if(cmd == GoIdle){
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth1);
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emmcclk(Initfreq);
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WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth1);
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usdhcclk(Initfreq);
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}
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if(r[Status] & Cmdinhibit){
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print("emmccmd: need to reset Cmdinhibit intr %ux stat %ux\n",
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r[Interrupt], r[Status]);
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WR(Control1, r[Control1] | Srstcmd);
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while(r[Control1] & Srstcmd)
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if(RR(Status) & Cmdinhibit){
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print("usdhccmd: need to reset Cmdinhibit intr %ux stat %ux\n",
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RR(Interrupt), RR(Status));
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WR(Control1, RR(Control1) | Srstcmd);
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while(RR(Control1) & Srstcmd)
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;
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while(r[Status] & Cmdinhibit)
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while(RR(Status) & Cmdinhibit)
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;
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}
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if((r[Status] & Datinhibit) &&
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if((RR(Status) & Datinhibit) &&
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((c & Isdata) || (c & Respmask) == Resp48busy)){
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print("emmccmd: need to reset Datinhibit intr %ux stat %ux\n",
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r[Interrupt], r[Status]);
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WR(Control1, r[Control1] | Srstdata);
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while(r[Control1] & Srstdata)
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print("usdhccmd: need to reset Datinhibit intr %ux stat %ux\n",
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RR(Interrupt), RR(Status));
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WR(Control1, RR(Control1) | Srstdata);
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while(RR(Control1) & Srstdata)
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;
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while(r[Status] & Datinhibit)
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while(RR(Status) & Datinhibit)
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;
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}
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while(r[Status] & Datactive)
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while(RR(Status) & Datactive)
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;
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WR(Arg1, arg);
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if((i = (r[Interrupt] & ~Cardintr)) != 0){
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if((i = (RR(Interrupt) & ~Cardintr)) != 0){
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if(i != Cardinsert)
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print("emmc: before command, intr was %ux\n", i);
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print("usdhc: before command, intr was %ux\n", i);
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WR(Interrupt, i);
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}
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WR(Mixctrl, (r[Mixctrl] & ~MixCmdMask) | (c & MixCmdMask));
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WR(Mixctrl, (RR(Mixctrl) & ~MixCmdMask) | (c & MixCmdMask));
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WR(Cmdtm, c & ~0xFFFF);
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now = MACHP(0)->ticks;
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while(((i=r[Interrupt])&(Cmddone|Err)) == 0)
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while(((i=RR(Interrupt))&(Cmddone|Err)) == 0)
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if(MACHP(0)->ticks - now > HZ)
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break;
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if((i&(Cmddone|Err)) != Cmddone){
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if((i&~(Err|Cardintr)) != Ctoerr)
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print("emmc: cmd %ux arg %ux error intr %ux stat %ux\n", c, arg, i, r[Status]);
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print("usdhc: cmd %ux arg %ux error intr %ux stat %ux\n", c, arg, i, RR(Status));
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WR(Interrupt, i);
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if(r[Status]&Cmdinhibit){
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WR(Control1, r[Control1]|Srstcmd);
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while(r[Control1]&Srstcmd)
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if(RR(Status)&Cmdinhibit){
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WR(Control1, RR(Control1)|Srstcmd);
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while(RR(Control1)&Srstcmd)
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;
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}
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error(Eio);
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@ -406,98 +402,95 @@ emmccmd(u32int cmd, u32int arg, u32int *resp)
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WR(Interrupt, i & ~(Datadone|Readrdy|Writerdy));
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switch(c & Respmask){
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case Resp136:
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resp[0] = r[Resp0]<<8;
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resp[1] = r[Resp0]>>24 | r[Resp1]<<8;
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resp[2] = r[Resp1]>>24 | r[Resp2]<<8;
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resp[3] = r[Resp2]>>24 | r[Resp3]<<8;
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resp[0] = RR(Resp0)<<8;
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resp[1] = RR(Resp0)>>24 | RR(Resp1)<<8;
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resp[2] = RR(Resp1)>>24 | RR(Resp2)<<8;
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resp[3] = RR(Resp2)>>24 | RR(Resp3)<<8;
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break;
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case Resp48:
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case Resp48busy:
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resp[0] = r[Resp0];
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resp[0] = RR(Resp0);
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break;
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case Respnone:
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resp[0] = 0;
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break;
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}
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if((c & Respmask) == Resp48busy){
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WR(Irpten, r[Irpten]|Datadone|Err);
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tsleep(&emmc.r, datadone, 0, 1000);
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i = r[Interrupt];
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WR(Irpten, RR(Irpten)|Datadone|Err);
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tsleep(&usdhc.r, datadone, 0, 1000);
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i = RR(Interrupt);
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if((i & Datadone) == 0)
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print("emmcio: no Datadone in %x after CMD%d\n", i, cmd);
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print("usdhcio: no Datadone in %x after CMD%d\n", i, cmd);
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if(i & Err)
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print("emmcio: CMD%d error interrupt %ux\n",
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cmd, r[Interrupt]);
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print("usdhcio: CMD%d error interrupt %ux\n",
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cmd, RR(Interrupt));
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if(i != 0) WR(Interrupt, i);
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}
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/*
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* Once card is selected, use faster clock
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*/
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if(cmd == MMCSelect){
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emmcclk(SDfreq);
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emmc.fastclock = 1;
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usdhcclk(SDfreq);
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usdhc.fastclock = 1;
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}
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if(cmd == Setbuswidth){
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if(emmc.appcmd){
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if(usdhc.appcmd){
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/*
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* If card bus width changes, change host bus width
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*/
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switch(arg){
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case 0:
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth1);
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WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth1);
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break;
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case 2:
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth4);
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WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth4);
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break;
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}
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}
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}else if(cmd == IORWdirect && (arg & ~0xFF) == (1<<31|0<<28|7<<9)){
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switch(arg & 0x3){
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case 0:
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth1);
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WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth1);
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break;
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case 2:
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WR(Control0, (r[Control0] & ~DwidthMask) | Dwidth4);
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WR(Control0, (RR(Control0) & ~DwidthMask) | Dwidth4);
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break;
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}
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}
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emmc.appcmd = (cmd == Appcmd);
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usdhc.appcmd = (cmd == Appcmd);
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return 0;
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}
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static void
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emmciosetup(int write, void *buf, int bsize, int bcount)
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usdhciosetup(int write, void *buf, int bsize, int bcount)
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{
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int len;
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len = bsize * bcount;
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int len = bsize * bcount;
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assert(((uintptr)buf&3) == 0);
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assert((len&3) == 0);
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assert(bsize <= 2048);
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WR(Blksizecnt, bcount<<16 | bsize);
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if(emmc.dma)
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sdfree(emmc.dma);
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emmc.dma = dmaalloc(buf, len);
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if(usdhc.dma)
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sdfree(usdhc.dma);
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usdhc.dma = dmaalloc(buf, len);
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if(write)
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cachedwbse(buf, len);
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else
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cachedwbinvse(buf, len);
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WR(Dmadesc, PADDR(emmc.dma));
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WR(Dmadesc, PADDR(usdhc.dma));
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}
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static void
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emmcio(int write, uchar *buf, int len)
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usdhcio(int write, uchar *buf, int len)
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{
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u32int *r = (u32int*)EMMCREGS;
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int i;
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u32int i;
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WR(Irpten, r[Irpten] | Datadone|Err);
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tsleep(&emmc.r, datadone, 0, 3000);
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WR(Irpten, r[Irpten] & ~(Datadone|Err));
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i = r[Interrupt];
|
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WR(Irpten, RR(Irpten) | Datadone|Err);
|
||||
tsleep(&usdhc.r, datadone, 0, 3000);
|
||||
WR(Irpten, RR(Irpten) & ~(Datadone|Err));
|
||||
i = RR(Interrupt);
|
||||
if((i & (Datadone|Err)) != Datadone){
|
||||
print("sdhc: %s error intr %ux stat %ux\n",
|
||||
write? "write" : "read", i, r[Status]);
|
||||
write? "write" : "read", i, RR(Status));
|
||||
WR(Interrupt, i);
|
||||
error(Eio);
|
||||
}
|
||||
|
|
@ -507,24 +500,22 @@ emmcio(int write, uchar *buf, int len)
|
|||
}
|
||||
|
||||
static void
|
||||
mmcinterrupt(Ureg*, void*)
|
||||
usdhcinterrupt(Ureg*, void*)
|
||||
{
|
||||
u32int *r;
|
||||
int i;
|
||||
u32int i;
|
||||
|
||||
r = (u32int*)EMMCREGS;
|
||||
i = r[Interrupt];
|
||||
i = RR(Interrupt);
|
||||
if(i&(Datadone|Err))
|
||||
wakeup(&emmc.r);
|
||||
WR(Irpten, r[Irpten] & ~i);
|
||||
wakeup(&usdhc.r);
|
||||
WR(Irpten, RR(Irpten) & ~i);
|
||||
}
|
||||
|
||||
SDio sdio = {
|
||||
"usdhc",
|
||||
emmcinit,
|
||||
emmcenable,
|
||||
emmcinquiry,
|
||||
emmccmd,
|
||||
emmciosetup,
|
||||
emmcio,
|
||||
usdhcinit,
|
||||
usdhcenable,
|
||||
usdhcinquiry,
|
||||
usdhccmd,
|
||||
usdhciosetup,
|
||||
usdhcio,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue