bcm64: do not use OTP_BOOTMODE_REG to determine OSC frequency (thanks richard miller)

the register does not seem to be accessible on the Rpi 3b.
so instead hardcode oscfreq in the Soc structure.

sys/src/9/bcm64/archbcm3.c

@@ -24,6 +24,7 @@ Soc soc = {
 	.physio		= 0x3F000000,
 	.virtio		= VIRTIO,
 	.armlocal	= 0x40000000,
+	.oscfreq	= 19200000,
 };
 
 enum {

sys/src/9/bcm64/archbcm4.c

@@ -25,6 +25,7 @@ Soc soc = {
 	.virtio		= VIRTIO2,
 	.armlocal	= 0xFF800000,
 	.pciwin		= 0x0600000000ULL,
+	.oscfreq	= 54000000,
 };
 
 enum {

sys/src/9/bcm64/clock.c

@@ -121,23 +121,15 @@ clockinit(void)
 
 	syswr(CNTP_TVAL_EL0, ~0UL);
 	if(m->machno == 0){
-		int oscfreq;
-
 		syswr(CNTP_CTL_EL0, Imask);
 
 		*(u32int*)(ARMLOCAL + GPUirqroute) = 0;
 
-		/* bit 1 from OTP bootmode register determines OSC frequency */
-		if(*((u32int*)(VIRTIO+0x20f000)) & (1<<1))
-			oscfreq = 19200000;
-		else
-			oscfreq = 54000000;
-
 		/* input clock to OSC */
 		*(u32int*)(ARMLOCAL + Localctl) = 0;
 
 		/* divide by (2^31/Prescaler) */
-		*(u32int*)(ARMLOCAL + Prescaler) = (((uvlong)SystimerFreq<<31)/oscfreq)&~1UL;
+		*(u32int*)(ARMLOCAL + Prescaler) = (((uvlong)SystimerFreq<<31)/soc.oscfreq)&~1UL;
 	} else {
 		syswr(CNTP_CTL_EL0, Enable);
 		intrenable(IRQcntpns, localclockintr, nil, BUSUNKNOWN, "clock");

sys/src/9/bcm64/dat.h

@@ -250,6 +250,7 @@ struct Soc {			/* SoC dependent configuration */
 	uintptr	virtio;
 	uintptr	armlocal;
 	uintptr	pciwin;
+	int	oscfreq;
 };
 extern Soc soc;