5l: fix shifts by zero
on arm32, we can do one of 4 shifts by a constant: reg<<(0..31) reg>>(1..32) ((u32int)reg)>>(1..32) reg ROT (0..31) There's no way to encode a 0 bit right shift, so when encoding reg>>0, flip it to the equivalent nop reg<<0, which can be encoded.
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@ -785,7 +785,10 @@ PP = p;
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case 8: /* sll $c,[R],R -> mov (R<<$c),R */
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case 8: /* sll $c,[R],R -> mov (R<<$c),R */
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aclass(&p->from);
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aclass(&p->from);
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o1 = oprrr(p->as, p->scond);
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if((p->as == ASRL || p->as == ASRA) && instoffset == 0)
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o1 = oprrr(ASLL, p->scond);
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else
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o1 = oprrr(p->as, p->scond);
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r = p->reg;
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r = p->reg;
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if(r == NREG)
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if(r == NREG)
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r = p->to.reg;
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r = p->to.reg;
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