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5l: fix shifts by zero

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on arm32, we can do one of 4 shifts
by a constant:

	reg<<(0..31)
	reg>>(1..32)
	((u32int)reg)>>(1..32)
	reg ROT (0..31)

There's no way to encode a 0 bit right
shift,  so when encoding reg>>0, flip
it to the equivalent nop reg<<0, which
can be encoded.
This commit is contained in:
Ori Bernstein 2021-01-23 20:36:09 -08:00
parent f76e28cb71
commit 5b8b5884f4
1 changed files with 4 additions and 1 deletions
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5
sys/src/cmd/5l/asm.c
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@ -785,7 +785,10 @@ PP = p;
case 8: /* sll $c,[R],R -> mov (R<<$c),R */
aclass(&p->from);
o1 = oprrr(p->as, p->scond);
if((p->as == ASRL || p->as == ASRA) && instoffset == 0)
o1 = oprrr(ASLL, p->scond);
else
o1 = oprrr(p->as, p->scond);
r = p->reg;
if(r == NREG)
r = p->to.reg;