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uartimx: fix interrupts

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need to turn off transmitter fifo interrupt when we run out of
data to transmit, and set rx fifo ready fifo threshold to one.
This commit is contained in:
cinap_lenrek 2022-05-09 17:22:00 +00:00 committed by xfnw
parent cb8e638d2a
commit 5a7ed2e652
1 changed files with 9 additions and 6 deletions
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15
sys/src/9/imx8/uartimx.c
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@ -166,13 +166,16 @@ kick(Uart *u)
{ {
u32int *regs = (u32int*)u->regs; u32int *regs = (u32int*)u->regs;
if(u->blocked) while(u->op < u->oe || uartstageoutput(u)){
return; if(u->blocked)
while(regs[USR1] & SR1_TRDY){
if(u->op >= u->oe && uartstageoutput(u) == 0)
break; break;
if((regs[USR1] & SR1_TRDY) == 0){
regs[UCR1] |= CR1_TRDYEN;
return;
}
regs[UTXD] = *(u->op++) & TX_DATA; regs[UTXD] = *(u->op++) & TX_DATA;
} }
regs[UCR1] &= ~CR1_TRDYEN;
} }
static void static void
@ -195,11 +198,11 @@ config(Uart *u)
regs[UCR4] = 31<<CR4_CTSTL_SHIFT; regs[UCR4] = 31<<CR4_CTSTL_SHIFT;
/* baud = clock / (16 * (ubmr+1)/(ubir+1)) */ /* baud = clock / (16 * (ubmr+1)/(ubir+1)) */
regs[UFCR] = (6 - 1)<<FCR_RFDIV_SHIFT | 32<<FCR_TXTL_SHIFT | 32<<FCR_RXTL_SHIFT; regs[UFCR] = (6 - 1)<<FCR_RFDIV_SHIFT | 16<<FCR_TXTL_SHIFT | 1<<FCR_RXTL_SHIFT;
regs[UBIR] = ((16*u->baud) / 1600)-1; regs[UBIR] = ((16*u->baud) / 1600)-1;
regs[UBMR] = (u->freq / 1600)-1; regs[UBMR] = (u->freq / 1600)-1;
regs[UCR1] = CR1_UARTEN | CR1_TRDYEN | CR1_RRDYEN; regs[UCR1] = CR1_UARTEN | CR1_RRDYEN;
} }
static int static int