cyclone v kernel: fpga support, fix CONFADDR
This commit is contained in:
aiju
parent
7cf8369411
commit
561346d07f
8 changed files with 483 additions and 269 deletions
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@ -2,7 +2,7 @@ dev
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root
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cons
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swap
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# arch
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arch
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uart
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mnt
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srv
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@ -24,6 +24,7 @@ dev
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segment
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link
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dma
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ethercycv
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ethermedium
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loopbackmedium
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@ -13,6 +13,7 @@ typedef struct Proc Proc;
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typedef struct PMMU PMMU;
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typedef struct Ureg Ureg;
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typedef struct ISAConf ISAConf;
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typedef struct DMAC DMAC;
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typedef uvlong Tval;
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#pragma incomplete Ureg
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@ -202,3 +203,7 @@ struct DevConf
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#define mpcore ((ulong*)MPCORE_BASE)
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#define resetmgr ((ulong*)RESETMGR_BASE)
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#define sysmgr ((ulong*)SYSMGR_BASE)
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/*dmacopy*/
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#define SRC_INC (1<<0)
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#define DST_INC (1<<14)
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@ -7,11 +7,44 @@
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#include "ureg.h"
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#include "../port/error.h"
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#define fpga ((ulong*) FPGAMGR_BASE)
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enum { Timeout = 3000 };
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enum {
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FPGASTAT,
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FPGACTRL,
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FPGAINTEN = 0x830/4,
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FPGAINTTYPE = 0x838/4,
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FPGAINTPOL = 0x83C/4,
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FPGAINTSTATUS = 0x840/4,
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FPGAEOI = 0x84C/4,
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FPGAPINS = 0x850/4,
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};
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enum {
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/*FPGACTRL*/
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HPSCONFIG = 1<<0,
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NCONFIGPULL = 1<<2,
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AXICFGEN = 1<<8,
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/*FPGAPINS*/
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NSTATUS = 1<<0,
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CONF_DONE = 1<<1,
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INIT_DONE = 1<<2,
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CRC_ERROR = 1<<3,
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CVP_CONF_DONE = 1<<4,
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PR_READY = 1<<5,
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PR_ERROR = 1<<6,
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PR_DONE = 1<<7,
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NCONFIG_PIN = 1<<8,
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NSTATUS_PIN = 1<<9,
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CONF_DONE_PIN = 1<<10,
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FPGA_POWER_ON = 1<<11
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};
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enum {
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Qdir = 0,
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Qtemp,
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Qpl,
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Qfbctl,
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Qfpga,
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Qbase,
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Qmax = 16,
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@ -19,288 +52,149 @@ enum {
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static Dirtab archdir[Qmax] = {
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".", { Qdir, 0, QTDIR }, 0, 0555,
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"temp", { Qtemp, 0}, 0, 0440,
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"pl", { Qpl, 0 }, 0, 0660,
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"fbctl", { Qfbctl, 0 }, 0, 0660,
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"fpga", { Qfpga, 0 }, 0, 0660,
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};
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static int narchdir = Qbase;
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static int temp = -128;
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static ulong *devc;
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static int dmadone;
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enum { PLBUFSIZ = 8192 };
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static uchar *plbuf;
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static Rendez plinitr, pldoner, pldmar;
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static QLock plrlock, plwlock;
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static Ref plwopen;
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static Physseg *axi;
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enum {
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DEVCTRL = 0,
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DEVISTS = 0xc/4,
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DEVMASK,
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DEVSTS,
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DMASRC = 0x18/4,
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DMADST,
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DMASRCL,
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DMADSTL,
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XADCCFG = 0x100/4,
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XADCSTS,
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XADCMASK,
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XADCMSTS,
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XADCCMD,
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XADCREAD,
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XADCMCTL,
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FPGA0_CLK_CTRL = 0x170/4,
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};
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enum {
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PROG = 1<<30,
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DONE = 1<<2,
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INITPE = 1<<1,
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INIT = 1<<4,
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DMADONE = 1<<13,
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};
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static void
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scram(void)
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{
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splhi();
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slcr[0x100/4] |= 1<<4;
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slcr[0x104/4] |= 1<<4;
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slcr[0x108/4] |= 1<<4;
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slcr[DEVCTRL] &= ~PROG;
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slcr[0x244/4] = 1<<4|1<<5;
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}
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static void
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xadcirq(Ureg *, void *)
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{
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int v;
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static int al, notfirst;
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while((devc[XADCMSTS] & 1<<8) == 0){
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v = ((u16int)devc[XADCREAD]) >> 4;
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if(v == 0){
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if(notfirst)
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print("temperature sensor reads 0, shouldn't happen\n");
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break;
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}
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notfirst = 1;
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temp = v * 5040 / 4096 - 2732;
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if(temp >= 800){
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if(al == 0)
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print("temperature exceeds 80 deg C\n");
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al = 1;
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}
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if(temp <= 750)
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al = 0;
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if(temp >= 900){
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print("chip temperature exceeds 90 deg C, shutting down");
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scram();
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}
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}
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devc[XADCSTS] = -1;
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}
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static void
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xadctimer(void)
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{
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devc[XADCCMD] = 1<<26 | 0<<16;
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}
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static void
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xadcinit(void)
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{
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int i;
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int x;
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devc = vmap(DEVC_BASE, 0x11C);
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devc[XADCMCTL] |= 1<<4;
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devc[XADCMCTL] &= ~(1<<4);
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devc[XADCCMD] = 0x08030000;
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for(i = 0; i < 15; i++)
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devc[XADCCMD] = 0;
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while((devc[XADCMSTS] & 1<<10) == 0)
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;
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while((devc[XADCMSTS] & 1<<8) == 0){
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x = devc[XADCREAD];
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USED(x);
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}
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devc[XADCCFG] = 0x80001114;
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devc[XADCMASK] = ~(1<<8);
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devc[XADCSTS] = -1;
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intrenable(XADCIRQ, xadcirq, nil, LEVEL, "xadc");
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addclock0link(xadctimer, XADCINTERVAL);
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}
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static Ref fpgawopen;
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enum { FPGABUFSIZ = 65536 };
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static uchar *fpgabuf;
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static int fpgabufp;
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static int fpgaok;
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static Rendez fpgarend;
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static u32int fpgawaitset, fpgawaitclr;
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static int
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isplinit(void *)
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donewaiting(void *)
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{
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return devc[DEVSTS] & INIT;
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u32int s;
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s = fpga[FPGAPINS];
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return (s & fpgawaitset | ~s & fpgawaitclr) != 0;
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}
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static void
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fpgairq(Ureg *, void *)
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{
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fpga[FPGAEOI] = -1;
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if(donewaiting(nil))
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wakeup(&fpgarend);
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}
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static int
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ispldone(void *)
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fpgawait(u32int set, u32int clr, int timeout)
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{
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return devc[DEVISTS] & DONE;
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}
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int s;
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static int
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isdmadone(void *)
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{
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return dmadone;
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fpgawaitset = set;
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fpgawaitclr = clr;
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if(donewaiting(nil)) return 0;
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s = spllo();
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fpga[FPGAINTEN] = 0;
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fpga[FPGAEOI] = -1;
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fpga[FPGAINTPOL] = set;
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fpga[FPGAINTEN] = set | clr;
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tsleep(&fpgarend, donewaiting, nil, timeout);
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fpga[FPGAINTEN] = 0;
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fpga[FPGAEOI] = -1;
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splx(s);
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return donewaiting(nil) ? 0 : -1;
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}
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static void
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plirq(Ureg *, void *)
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fpgaconf(void)
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{
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ulong fl;
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int msel;
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enum { PORFAST = 1, AES = 2, AESMAYBE = 4, COMP = 8, FPP32 = 16 };
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static uchar mseltab[16][3] = {
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[0] {0, 1, PORFAST},
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[4] {0, 1, 0},
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[1] {0, 2, PORFAST|AES},
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[5] {0, 2, AES},
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[2] {0, 3, COMP|AESMAYBE|PORFAST},
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[6] {0, 3, COMP|AESMAYBE},
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[8] {1, 1, PORFAST|FPP32},
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[12] {1, 1, FPP32},
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[9] {1, 2, AES|FPP32|PORFAST},
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[13] {1, 2, AES|FPP32},
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[10] {1, 4, COMP|AESMAYBE|PORFAST|FPP32},
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[14] {1, 4, COMP|AESMAYBE|FPP32}
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};
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fl = devc[DEVISTS];
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if((fl & INITPE) != 0)
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wakeup(&plinitr);
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if((fl & DONE) != 0){
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slcr[0x900/4] = 0xf;
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slcr[0x240/4] = 0;
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devc[DEVMASK] |= DONE;
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axi->attr &= ~SG_FAULT;
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wakeup(&pldoner);
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if((fpga[FPGAPINS] & FPGA_POWER_ON) == 0)
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error("FPGA powered off");
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msel = fpga[FPGASTAT] >> 3 & 0x1f;
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if(msel >= 16 || mseltab[msel][1] == 0){
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print("MSEL set to invalid setting %#.2x\n", msel);
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error("MSEL set to invalid setting");
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}
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if((fl & DMADONE) != 0){
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dmadone++;
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wakeup(&pldmar);
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}
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devc[DEVISTS] = fl;
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fpga[FPGACTRL] = fpga[FPGACTRL] & ~0x3ff
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| mseltab[msel][0] << 9 /* cfgwdth */
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| mseltab[msel][1]-1 << 6 /* cdratio */
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| NCONFIGPULL | HPSCONFIG;
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if(fpgawait(0, NSTATUS, Timeout) < 0 || fpgawait(0, CONF_DONE, Timeout) < 0)
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error("FPGA won't enter reset phase");
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fpga[FPGACTRL] &= ~NCONFIGPULL;
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if(fpgawait(NSTATUS, 0, Timeout) < 0)
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error("FPGA won't enter configuration phase");
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fpga[FPGACTRL] |= AXICFGEN;
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}
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static void
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plinit(void)
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fpgawrite(uchar *a, int n)
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{
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Physseg seg;
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int m;
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memset(&seg, 0, sizeof seg);
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seg.attr = SG_PHYSICAL | SG_DEVICE | SG_NOEXEC | SG_FAULT;
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seg.name = "axi";
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seg.pa = 0x40000000;
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seg.size = 0x8000000;
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axi = addphysseg(&seg);
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devc[DEVCTRL] &= ~(PROG|1<<25);
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devc[DEVCTRL] |= 3<<26|PROG;
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devc[DEVISTS] = -1;
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devc[DEVMASK] = ~(DONE|INITPE|DMADONE);
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intrenable(DEVCIRQ, plirq, nil, LEVEL, "pl");
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slcr[FPGA0_CLK_CTRL] = 1<<20 | 10<<8;
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}
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static void
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plconf(void)
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{
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axi->attr |= SG_FAULT;
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procflushpseg(axi);
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flushmmu();
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slcr[0x240/4] = 0xf;
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slcr[0x900/4] = 0xa;
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devc[DEVISTS] = DONE|INITPE|DMADONE;
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devc[DEVCTRL] |= PROG;
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devc[DEVCTRL] &= ~PROG;
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devc[DEVMASK] &= ~DONE;
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devc[DEVCTRL] |= PROG;
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while(waserror())
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;
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sleep(&plinitr, isplinit, nil);
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poperror();
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}
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static long
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plwrite(uintptr pa, long n)
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{
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dmadone = 0;
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coherence();
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devc[DMASRC] = pa;
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devc[DMADST] = -1;
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devc[DMASRCL] = n>>2;
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devc[DMADSTL] = 0;
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while(waserror())
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;
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sleep(&pldmar, isdmadone, nil);
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poperror();
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return n;
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}
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static long
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plcopy(uchar *d, long n)
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{
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long ret;
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ulong nn;
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uintptr pa;
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if((n & 3) != 0 || n <= 0)
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error(Eshort);
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eqlock(&plwlock);
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if(waserror()){
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qunlock(&plwlock);
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fpgaok = 0;
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nexterror();
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}
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ret = n;
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pa = PADDR(plbuf);
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while(n > 0){
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if(n > PLBUFSIZ)
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nn = PLBUFSIZ;
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else
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nn = n;
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memmove(plbuf, d, nn);
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cleandse(plbuf, plbuf + nn);
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clean2pa(pa, pa + nn);
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n -= plwrite(pa, nn);
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if((fpga[FPGAPINS] & NSTATUS) == 0)
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error("FPGA reports configuration error");
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fpgaok = 1;
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while(fpgabufp + n >= FPGABUFSIZ){
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m = FPGABUFSIZ - fpgabufp;
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memmove(&fpgabuf[fpgabufp], a, m);
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cleandse(fpgabuf, fpgabuf + FPGABUFSIZ);
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dmacopy((void *) FPGAMGRDATA, fpgabuf, FPGABUFSIZ, SRC_INC);
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a += m;
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n -= m;
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fpgabufp = 0;
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}
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qunlock(&plwlock);
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memmove(&fpgabuf[fpgabufp], a, n);
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fpgabufp += n;
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poperror();
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return ret;
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}
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void
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archinit(void)
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static void
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fpgafinish(void)
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{
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slcr[2] = 0xDF0D;
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xadcinit();
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plinit();
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if(!fpgaok) return;
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while((fpgabufp & 3) != 0)
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fpgabuf[fpgabufp++] = 0;
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cleandse(fpgabuf, fpgabuf + fpgabufp);
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dmacopy((void *) FPGAMGRDATA, fpgabuf, fpgabufp, SRC_INC);
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fpga[FPGACTRL] &= ~AXICFGEN;
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if(fpgawait(CONF_DONE, NSTATUS, Timeout) < 0){
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print("FPGA stuck in configuration phase -- truncated file?\n");
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return;
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}
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if((fpga[FPGAPINS] & NSTATUS) == 0){
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print("FPGA reports configuration error\n");
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return;
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}
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if(fpgawait(INIT_DONE, 0, Timeout) < 0){
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print("FPGA stuck in initialization phase\n");
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return;
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}
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fpga[FPGACTRL] &= ~HPSCONFIG;
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}
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static long
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archread(Chan *c, void *a, long n, vlong offset)
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archread(Chan *c, void *a, long n, vlong)
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{
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char buf[64];
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switch((ulong)c->qid.path){
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case Qdir:
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return devdirread(c, a, n, archdir, narchdir, devgen);
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case Qtemp:
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snprint(buf, sizeof(buf), "%d.%d\n", temp/10, temp%10);
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return readstr(offset, a, n, buf);
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case Qpl:
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eqlock(&plrlock);
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if(waserror()){
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qunlock(&plrlock);
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nexterror();
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}
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sleep(&pldoner, ispldone, nil);
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qunlock(&plrlock);
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poperror();
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return 0;
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case Qfbctl:
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return fbctlread(c, a, n, offset);
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default:
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error(Egreg);
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return -1;
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@ -308,13 +202,12 @@ archread(Chan *c, void *a, long n, vlong offset)
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}
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static long
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archwrite(Chan *c, void *a, long n, vlong offset)
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archwrite(Chan *c, void *a, long n, vlong)
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{
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switch((ulong)c->qid.path){
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case Qpl:
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return plcopy(a, n);
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case Qfbctl:
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return fbctlwrite(c, a, n, offset);
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case Qfpga:
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fpgawrite(a, n);
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return n;
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default:
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error(Egreg);
|
||||
return -1;
|
||||
|
|
@ -337,14 +230,16 @@ static Chan*
|
|||
archopen(Chan* c, int omode)
|
||||
{
|
||||
devopen(c, omode, archdir, narchdir, devgen);
|
||||
if((ulong)c->qid.path == Qpl && (c->mode == OWRITE || c->mode == ORDWR)){
|
||||
if(incref(&plwopen) != 1){
|
||||
if((ulong)c->qid.path == Qfpga && (c->mode == OWRITE || c->mode == ORDWR)){
|
||||
if(incref(&fpgawopen) != 1){
|
||||
c->flag &= ~COPEN;
|
||||
decref(&plwopen);
|
||||
decref(&fpgawopen);
|
||||
error(Einuse);
|
||||
}
|
||||
plbuf = smalloc(PLBUFSIZ);
|
||||
plconf();
|
||||
fpgaok = 0;
|
||||
fpgaconf();
|
||||
fpgabuf = xspanalloc(FPGABUFSIZ, 64, 0);
|
||||
fpgabufp = 0;
|
||||
}
|
||||
return c;
|
||||
}
|
||||
|
|
@ -353,13 +248,23 @@ static void
|
|||
archclose(Chan* c)
|
||||
{
|
||||
if((c->flag & COPEN) != 0)
|
||||
if((ulong)c->qid.path == Qpl && (c->mode == OWRITE || c->mode == ORDWR)){
|
||||
free(plbuf);
|
||||
plbuf = nil;
|
||||
decref(&plwopen);
|
||||
if((ulong)c->qid.path == Qfpga && (c->mode == OWRITE || c->mode == ORDWR)){
|
||||
fpgafinish();
|
||||
//xfree(fpgabuf);
|
||||
fpgabuf = nil;
|
||||
decref(&fpgawopen);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
archreset(void)
|
||||
{
|
||||
fpga[FPGAINTEN] = 0;
|
||||
fpga[FPGAEOI] = -1;
|
||||
fpga[FPGAINTTYPE] = -1;
|
||||
intrenable(FPGAMGRIRQ, fpgairq, nil, LEVEL, "fpgamgr");
|
||||
}
|
||||
|
||||
static Chan*
|
||||
archattach(char* spec)
|
||||
{
|
||||
|
|
@ -370,7 +275,7 @@ Dev archdevtab = {
|
|||
'P',
|
||||
"arch",
|
||||
|
||||
devreset,
|
||||
archreset,
|
||||
devinit,
|
||||
devshutdown,
|
||||
archattach,
|
||||
|
|
|
|||
265
sys/src/9/cycv/dma.c
Normal file
265
sys/src/9/cycv/dma.c
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
#include "u.h"
|
||||
#include "../port/lib.h"
|
||||
#include "mem.h"
|
||||
#include "dat.h"
|
||||
#include "fns.h"
|
||||
#include "io.h"
|
||||
#include "ureg.h"
|
||||
#include "../port/error.h"
|
||||
|
||||
#define dmar ((ulong*)DMAS_BASE)
|
||||
|
||||
enum {
|
||||
DSR = 0x000,
|
||||
DPC = 0x004/4,
|
||||
INTEN = 0x20 / 4,
|
||||
INT_EVENT_RIS = 0x024 / 4,
|
||||
INTMIS = 0x028 / 4,
|
||||
INTCLR = 0x02C / 4,
|
||||
FSRD = 0x030 / 4,
|
||||
FSRC = 0x034 / 4,
|
||||
FTRD = 0x038 / 4,
|
||||
DBGSTATUS = 0xD00 / 4,
|
||||
DBGCMD = 0xD04 / 4,
|
||||
DBGINST0 = 0xD08 / 4,
|
||||
DBGINST1 = 0xD0C / 4,
|
||||
CR0 = 0xE00 / 4,
|
||||
CR1, CR2, CR3, CR4, CRD,
|
||||
WD = 0xE80 / 4,
|
||||
};
|
||||
enum {
|
||||
DMAStopped,
|
||||
DMAExecuting,
|
||||
DMACacheMiss,
|
||||
DMAUpdatingPC,
|
||||
DMAWaitingForEvent,
|
||||
DMAAtBarrier,
|
||||
DMAWaitingForPeripheral = 7,
|
||||
DMAKilling,
|
||||
DMACompleting,
|
||||
DMAFaultingCompleting=14,
|
||||
DMAFaulting,
|
||||
};
|
||||
#define FTR(n) dmar[(0x40/4 + (n))]
|
||||
#define CSR(n) dmar[(0x100/4 + (n)*2)]
|
||||
#define CPC(n) dmar[(0x104/4 + (n)*2)]
|
||||
#define SAR(n) dmar[(0x400/4 + (n)*8)]
|
||||
#define DAR(n) dmar[(0x404/4 + (n)*8)]
|
||||
#define CCR(n) dmar[(0x408/4 + (n)*8)]
|
||||
#define LC0(n) dmar[(0x40C/4 + (n)*8)]
|
||||
#define LC1(n) dmar[(0x410/4 + (n)*8)]
|
||||
|
||||
#define DST_BURST(n) (((n)-1&0xf)<<18)
|
||||
#define DST_BEAT_1 (0)
|
||||
#define DST_BEAT_2 (1<<15)
|
||||
#define DST_BEAT_4 (2<<15)
|
||||
#define DST_BEAT_8 (3<<15)
|
||||
#define DST_BEAT_16 (4<<15)
|
||||
#define SRC_BURST(n) (((n)-1&0xf)<<4)
|
||||
#define SRC_BEAT_1 (0)
|
||||
#define SRC_BEAT_2 (1<<1)
|
||||
#define SRC_BEAT_4 (2<<1)
|
||||
#define SRC_BEAT_8 (3<<1)
|
||||
#define SRC_BEAT_16 (4<<1)
|
||||
|
||||
#define dmaMOV_SARn 0x00bc
|
||||
#define dmaMOV_CCRn 0x01bc
|
||||
#define dmaMOV_DARn 0x02bc
|
||||
#define dmaLP0(n) (((n)-1&0xff)<<8|0x20)
|
||||
#define dmaLP1(n) (((n)-1&0xff)<<8|0x22)
|
||||
#define dmaLPEND0(n) (((n)&0xff)<<8|0x38)
|
||||
#define dmaLPEND1(n) (((n)&0xff)<<8|0x3c)
|
||||
#define dmaLD 0x04
|
||||
#define dmaST 0x08
|
||||
#define dmaSEV(n) (((n)&31)<<11|0x34)
|
||||
#define dmaEND 0x00
|
||||
#define dmaWMB 0x13
|
||||
|
||||
static QLock dmalock;
|
||||
static Rendez dmarend;
|
||||
static int finished;
|
||||
static ulong code[64];
|
||||
|
||||
static int
|
||||
isfinished(void *)
|
||||
{
|
||||
return finished;
|
||||
}
|
||||
static void
|
||||
dmairq(Ureg *, void *)
|
||||
{
|
||||
dmar[INTCLR] = -1;
|
||||
finished = 1;
|
||||
wakeup(&dmarend);
|
||||
}
|
||||
|
||||
static void
|
||||
compactify(ulong *lp)
|
||||
{
|
||||
uchar *p, *q;
|
||||
|
||||
q = p = (uchar *) lp;
|
||||
for(;;){
|
||||
switch(*p){
|
||||
case 0xbc:
|
||||
q[0] = p[0];
|
||||
q[1] = p[1];
|
||||
q[2] = p[4];
|
||||
q[3] = p[5];
|
||||
q[4] = p[6];
|
||||
q[5] = p[7];
|
||||
q += 6; p += 8;
|
||||
break;
|
||||
case 0x20: case 0x22: case 0x38: case 0x3c: case 0x34:
|
||||
q[0] = p[0];
|
||||
q[1] = p[1];
|
||||
q += 2; p += 4;
|
||||
break;
|
||||
case 0x04: case 0x08: case 0x13:
|
||||
q[0] = p[0];
|
||||
q++; p += 4;
|
||||
break;
|
||||
case 0x00:
|
||||
q[0] = 0;
|
||||
return;
|
||||
default:
|
||||
panic("DMA: unknown opcode %.2x", *p);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define BURST(n) *p++ = dmaMOV_CCRn, *p++ = DST_BEAT_4 | SRC_BEAT_4 | SRC_BURST(n) | DST_BURST(n) | attr
|
||||
|
||||
void
|
||||
dmacopy(void *dst, void *src, ulong n, int attr)
|
||||
{
|
||||
ulong *p;
|
||||
|
||||
assert((n & 3) == 0 && ((uintptr)src & 3) == 0 && ((uintptr)dst & 3) == 0);
|
||||
while(n > (1<<22)){
|
||||
dmacopy(dst, src, 1<<22, attr);
|
||||
if((attr & SRC_INC) != 0) src = (uchar*)src + (1<<22);
|
||||
if((attr & DST_INC) != 0) dst = (uchar*)dst + (1<<22);
|
||||
}
|
||||
if(n == 0) return;
|
||||
qlock(&dmalock);
|
||||
p = code;
|
||||
*p++ = dmaMOV_SARn; *p++ = PADDR(src);
|
||||
*p++ = dmaMOV_DARn; *p++ = PADDR(dst);
|
||||
if((n >> 6) >= 1){
|
||||
BURST(16);
|
||||
if((n>>14) >= 1){
|
||||
if((n>>14) > 1) *p++ = dmaLP0(n >> 14);
|
||||
*p++ = dmaLP1(256);
|
||||
*p++ = dmaLD;
|
||||
*p++ = dmaST;
|
||||
*p++ = dmaLPEND1(2);
|
||||
if((n>>14) > 1) *p++ = dmaLPEND0(6);
|
||||
n &= (1<<14)-1;
|
||||
}
|
||||
if((n >> 6) >= 1){
|
||||
if((n>>6) > 1) *p++ = dmaLP0(n >> 6);
|
||||
*p++ = dmaLD;
|
||||
*p++ = dmaST;
|
||||
if((n>>6) > 1) *p++ = dmaLPEND0(2);
|
||||
n &= 63;
|
||||
}
|
||||
}
|
||||
if(n >= 4){
|
||||
BURST(n>>2);
|
||||
*p++ = dmaLD;
|
||||
*p++ = dmaST;
|
||||
}
|
||||
*p++ = dmaWMB;
|
||||
*p++ = dmaSEV(0);
|
||||
*p = dmaEND;
|
||||
compactify(code);
|
||||
if((CSR(0) & 0xf) != DMAStopped){
|
||||
while((dmar[DBGSTATUS] & 1) != 0)
|
||||
tsleep(&up->sleep, return0, nil, 1);
|
||||
dmar[DBGINST0] = 0x1 << 16 | 1;
|
||||
dmar[DBGCMD] = 0;
|
||||
while((dmar[DBGSTATUS] & 1) != 0)
|
||||
tsleep(&up->sleep, return0, nil, 1);
|
||||
while((CSR(0) & 0xf) != DMAStopped)
|
||||
tsleep(&up->sleep, return0, nil, 1);
|
||||
}
|
||||
cleandse(code, code + nelem(code));
|
||||
while((dmar[DBGSTATUS] & 1) != 0)
|
||||
tsleep(&up->sleep, return0, nil, 1);
|
||||
dmar[DBGINST0] = 0xa0 << 16;
|
||||
dmar[DBGINST1] = PADDR(code);
|
||||
finished = 0;
|
||||
dmar[DBGCMD] = 0;
|
||||
while(!finished)
|
||||
sleep(&dmarend, isfinished, nil);
|
||||
qunlock(&dmalock);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
dmaabort(Ureg *, void *)
|
||||
{
|
||||
int i;
|
||||
|
||||
if((dmar[FSRD] & 1) != 0){
|
||||
iprint("dma: manager fault: ");
|
||||
if((dmar[FTRD] & 1<<30) != 0)
|
||||
iprint("debug instruction, ");
|
||||
if((dmar[FTRD] & 1<<16) != 0)
|
||||
iprint("instruction fetch error, ");
|
||||
if((dmar[FTRD] & 1<<5) != 0)
|
||||
iprint("event security violation, ");
|
||||
if((dmar[FTRD] & 1<<4) != 0)
|
||||
iprint("DMAGO security violation, ");
|
||||
if((dmar[FTRD] & 1<<1) != 0)
|
||||
iprint("operand invalid, ");
|
||||
if((dmar[FTRD] & 1<<0) != 0)
|
||||
iprint("undefined instruction, ");
|
||||
iprint("\n");
|
||||
}
|
||||
for(i = 0; i < 8; i++){
|
||||
if((dmar[FSRC] & 1<<i) == 0)
|
||||
continue;
|
||||
iprint("dma: channel %d fault\n", i);
|
||||
iprint("code = %.8p, PC = %.8ulx\n", code, CPC(i));
|
||||
iprint("CCRn = %.8ulx, CSRn = %.8ulx\n", CCR(i), CSR(i));
|
||||
iprint("LC0 = %.2ulx, LC1 = %.2ulx\n", LC0(i), LC1(i));
|
||||
if((FTR(i) & 1<<31) != 0)
|
||||
iprint("insufficient resources, ");
|
||||
if((FTR(i) & 1<<30) != 0)
|
||||
iprint("debug instruction, ");
|
||||
if((FTR(i) & 1<<18) != 0)
|
||||
iprint("read error, ");
|
||||
if((FTR(i) & 1<<17) != 0)
|
||||
iprint("write error, ");
|
||||
if((FTR(i) & 1<<16) != 0)
|
||||
iprint("instruction fetch error, ");
|
||||
if((FTR(i) & 1<<13) != 0)
|
||||
iprint("FIFO underflow, ");
|
||||
if((FTR(i) & 1<<12) != 0)
|
||||
iprint("FIFO error, ");
|
||||
if((FTR(i) & 1<<7) != 0)
|
||||
iprint("CCRn security violation, ");
|
||||
if((FTR(i) & 1<<6) != 0)
|
||||
iprint("peripheral security violation, ");
|
||||
if((FTR(i) & 1<<5) != 0)
|
||||
iprint("event security violation, ");
|
||||
if((FTR(i) & 1<<4) != 0)
|
||||
iprint("DMAGO security violation, ");
|
||||
if((FTR(i) & 1<<1) != 0)
|
||||
iprint("operand invalid, ");
|
||||
if((FTR(i) & 1<<0) != 0)
|
||||
iprint("undefined instruction, ");
|
||||
iprint("\n");
|
||||
}
|
||||
panic("DMA fault");
|
||||
}
|
||||
|
||||
void
|
||||
dmalink(void)
|
||||
{
|
||||
dmar[INTEN] = 1;
|
||||
intrenable(DMAIRQ0, dmairq, nil, LEVEL, "dma");
|
||||
intrenable(DMAABORTIRQ, dmaabort, nil, LEVEL, "dma_abort");
|
||||
}
|
||||
|
|
@ -199,8 +199,6 @@ ethrx(Ether *edev)
|
|||
r = &c->rxr[4 * c->rxconsi];
|
||||
if((r[0] >> 31) != 0)
|
||||
break;
|
||||
if((r[0] & 1<<15) != 0)
|
||||
iprint("eth: error frame\n");
|
||||
if((r[0] & (3<<8)) != (3<<8))
|
||||
iprint("eth: lilu dallas multidescriptor\n");
|
||||
bp = c->rxs[c->rxconsi];
|
||||
|
|
@ -404,6 +402,38 @@ ethmcast(void *arg, uchar *ea, int on)
|
|||
}
|
||||
}
|
||||
|
||||
static long
|
||||
ethifstat(Ether *edev, void *a, long n, ulong offset)
|
||||
{
|
||||
static char *names[] = {
|
||||
"txoctetcount_gb", "txframecount_gb", "txbroadcastframes_g", "txmulticastframes_g",
|
||||
"tx64octets_gb", "tx65to127octets_gb", "tx128to255octets_gb", "tx256to511octets_gb",
|
||||
"tx512to1023octets_gb", "tx1024tomaxoctets_gb", "txunicastframes_gb", "txmulticastframes_gb",
|
||||
"txbroadcastframes_gb", "txunderflowerror", "txsinglecol_g", "txmulticol_g",
|
||||
"txdeferred", "txlatecol", "txexesscol", "txcarriererr",
|
||||
"txoctetcnt", "txframecount_g", "txexcessdef", "txpauseframes",
|
||||
"txvlanframes_g", "txoversize_g", "rxframecount_gb", "rxoctetcount_gb",
|
||||
"rxoctetcount_g", "rxbroadcastframes_g", "rxmulticastframes_g", "rxcrcerror",
|
||||
"rxalignmenterror", "rxrunterror", "rxjabbererror", "rxundersize_g",
|
||||
"rxoversize_g", "rx64octets_gb", "rx65to127octets_gb", "rx128to255octets_gb",
|
||||
"rx256to511octets_gb", "rx512to1023octets_gb", "rx1024tomaxoctets_gb", "rxunicastframes_g",
|
||||
"rxlengtherror", "rxoutofrangetype", "rxpauseframes", "rxfifooverflow",
|
||||
"rxvlanframes_gb", "rxwatchdogerror", "rxrcverror", "rxctrlframes_g",
|
||||
};
|
||||
int i;
|
||||
char *buf, *p, *e;
|
||||
Ctlr *c;
|
||||
|
||||
p = buf = smalloc(READSTR);
|
||||
e = p + READSTR;
|
||||
c = edev->ctlr;
|
||||
for(i = 0; i < nelem(names); i++)
|
||||
p = seprint(p, e, "%s: %lud\n", names[i], c->r[0x114/4 + i]);
|
||||
n = readstr(offset, a, n, buf);
|
||||
free(buf);
|
||||
return n;
|
||||
}
|
||||
|
||||
static int
|
||||
etherpnp(Ether *edev)
|
||||
{
|
||||
|
|
@ -425,6 +455,7 @@ etherpnp(Ether *edev)
|
|||
edev->mbps = 1000;
|
||||
edev->promiscuous = ethprom;
|
||||
edev->multicast = ethmcast;
|
||||
edev->ifstat = ethifstat;
|
||||
|
||||
if(ethinit(edev) < 0){
|
||||
edev->ctlr = nil;
|
||||
|
|
|
|||
|
|
@ -76,3 +76,4 @@ uintptr palookur(void *);
|
|||
void screeninit(void);
|
||||
int isaconfig(char*, int, ISAConf*);
|
||||
void cputhex(u32int);
|
||||
void dmacopy(void *, void *, ulong, int);
|
||||
|
|
|
|||
|
|
@ -5,7 +5,10 @@
|
|||
#define EMAC1_BASE 0xFF702000
|
||||
#define RESETMGR_BASE 0xFFD05000
|
||||
#define SYSMGR_BASE 0xFFD08000
|
||||
#define FPGAMGR_BASE 0xFF706000
|
||||
#define FPGAMGRDATA 0xFFB90000
|
||||
#define OCRAM 0xFFFF0000
|
||||
#define DMAS_BASE 0xFFE01000
|
||||
|
||||
/*RESETMGR*/
|
||||
#define PERMODRST (0x14/4)
|
||||
|
|
@ -17,6 +20,9 @@
|
|||
#define TIMERIRQ 29
|
||||
#define UART0IRQ 194
|
||||
#define EMAC1IRQ 152
|
||||
#define FPGAMGRIRQ 207
|
||||
#define DMAIRQ0 136
|
||||
#define DMAABORTIRQ 144
|
||||
|
||||
#define LEVEL 0
|
||||
#define EDGE 1
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ TEXT _start0(SB), $-4
|
|||
_clrstart:
|
||||
MOVW.P R0, 4(R1)
|
||||
CMP.S R1, R2
|
||||
BGE _clrstart
|
||||
BGT _clrstart
|
||||
|
||||
/* clean BSS */
|
||||
MOVW $edata-KZERO(SB), R1
|
||||
|
|
@ -45,7 +45,7 @@ _clrstart:
|
|||
_clrbss:
|
||||
MOVW.P R0, 4(R1)
|
||||
CMP.S R1, R2
|
||||
BGE _clrbss
|
||||
BGT _clrbss
|
||||
|
||||
PUTC('a')
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue