igfx: fix typo, initialize more lvds bits for G45, T60 testing
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990514f9f7
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54a1db15dc
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@ -304,8 +304,8 @@ devtype(Igfx *igfx)
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switch(igfx->pci->did){
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case 0x0166: /* X230 */
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return TypeIVB;
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case 0x2a42: /* X200s */
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case 0x27a2: /* T60 (testing) */
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case 0x2a42: /* X200 */
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return TypeG45;
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}
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return -1;
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@ -608,10 +608,6 @@ initdpll(Igfx *igfx, int x, int freq, int islvds, int ishdmi)
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/* VGA Mode Disable */
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dpll->ctrl.v |= (1<<28);
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/* P1 Post Divisor */
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dpll->ctrl.v &= ~0xFF00FF;
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dpll->ctrl.v |= 0x10001<<(p1-1);
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dpll->fp0.v &= ~(0x3f<<16);
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dpll->fp0.v |= n << 16;
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dpll->fp0.v &= ~(0x3f<<8);
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@ -619,7 +615,16 @@ initdpll(Igfx *igfx, int x, int freq, int islvds, int ishdmi)
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dpll->fp0.v &= ~(0x3f<<0);
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dpll->fp0.v |= m2 << 0;
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dpll->fp1.v = dpll->fp0.v;
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/* FP0 P1 Post Divisor */
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dpll->ctrl.v &= ~0xFF0000;
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dpll->ctrl.v |= 0x010000<<(p1-1);
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/* FP1 P1 Post divisor */
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if(igfx->pci->did != 0x27a2){
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dpll->ctrl.v &= ~0xFF;
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dpll->ctrl.v |= 0x01<<(p1-1);
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dpll->fp1.v = dpll->fp0.v;
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}
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return 0;
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}
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@ -776,6 +781,19 @@ init(Vga* vga, Ctlr* ctlr)
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x = (igfx->lvds.v >> 30) & 1;
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igfx->lvds.v |= (1<<31);
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igfx->ppcontrol.v |= 5;
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if(igfx->type == TypeG45){
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igfx->lvds.v &= ~(1<<24); /* data format select 18/24bpc */
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igfx->lvds.v &= ~(3<<20);
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if(m->hsync == '-')
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igfx->lvds.v ^= 1<<20;
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if(m->vsync == '-')
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igfx->lvds.v ^= 1<<21;
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igfx->lvds.v |= (1<<15); /* border enable */
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}
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} else {
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if(igfx->npipe > 2)
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x = (igfx->adpa.v >> 29) & 3;
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@ -786,14 +804,11 @@ init(Vga* vga, Ctlr* ctlr)
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igfx->adpa.v &= ~(3<<10); /* Monitor DPMS: on */
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igfx->adpa.v &= ~(1<<15); /* ADPA Polarity Select */
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if(m->vsync == '+')
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igfx->adpa.v |= 1<<4;
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else if(m->vsync == '-')
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igfx->adpa.v &= ~(1<<14);
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if(m->hsync == '+')
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igfx->adpa.v |= 1<<3;
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else if(m->hsync == '-')
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igfx->adpa.v &= ~(1<<3);
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igfx->adpa.v |= 3<<3;
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if(m->hsync == '-')
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igfx->adpa.v ^= 1<<3;
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if(m->vsync == '-')
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igfx->adpa.v ^= 1<<4;
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}
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}
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p = &igfx->pipe[x];
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