imx8: pcie and nvme support
This commit is contained in:
cinap_lenrek
parent
e39d924907
commit
548a48d156
8 changed files with 635 additions and 2 deletions
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@ -1075,6 +1075,90 @@ enablepll(int input)
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}
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}
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enum {
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CCM_ANALOG_PLLOUT_MONITOR_CFG = 0x74/4,
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PLLOUT_MONITOR_CLK_CKE = 1<<4,
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CCM_ANALOG_FRAC_PLLOUT_DIV_CFG = 0x78/4,
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CCM_ANALOG_SCCG_PLLOUT_DIV_CFG = 0x7C/4,
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};
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static struct {
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uchar input;
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uchar reg; /* divider register */
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uchar shift; /* divider shift */
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} anapllout_input[16] = {
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[0] OSC_25M_REF_CLK,
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[1] OSC_27M_REF_CLK,
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/* [2] HDMI_PHY_27M_CLK */
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/* [3] CLK1_P_N */
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[4] OSC_32K_REF_CLK,
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[5] AUDIO_PLL1_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 0,
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[6] AUDIO_PLL2_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 4,
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[7] GPU_PLL_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 12,
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[8] VPU_PLL_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 16,
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[9] VIDEO_PLL1_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 8,
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[10] ARM_PLL_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 20,
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[11] SYSTEM_PLL1_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 0,
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[12] SYSTEM_PLL2_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 4,
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[13] SYSTEM_PLL3_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 8,
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[14] VIDEO_PLL2_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 16,
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[15] DRAM_PLL1_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 12,
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};
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static void
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setanapllout(int input, int freq)
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{
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int mux, div, reg;
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for(mux = 0; mux < nelem(anapllout_input); mux++)
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if(anapllout_input[mux].input == input)
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goto Muxok;
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panic("setanapllout: bad input clock\n");
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return;
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Muxok:
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anatop[CCM_ANALOG_PLLOUT_MONITOR_CFG] = mux;
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if(freq <= 0)
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return;
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div = input_clk_freq[input] / freq;
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if(div < 1 || div > 8){
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panic("setanapllout: divider out of range\n");
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return;
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}
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enablepll(input);
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reg = anapllout_input[mux].reg;
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if(reg){
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int shift = anapllout_input[mux].shift;
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anatop[reg] = (anatop[reg] & ~(7<<shift)) | ((div-1)<<shift);
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} else if(div != 1){
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panic("setanapllout: bad frequency\n");
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return;
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}
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anatop[CCM_ANALOG_PLLOUT_MONITOR_CFG] |= PLLOUT_MONITOR_CLK_CKE;
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}
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static int
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getanapllout(void)
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{
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int mux, input, freq, reg, div;
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u32int cfg = anatop[CCM_ANALOG_PLLOUT_MONITOR_CFG];
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mux = cfg & 0xF;
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input = anapllout_input[mux].input;
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if(input == 0)
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return 0;
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freq = input_clk_freq[input];
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if((cfg & PLLOUT_MONITOR_CLK_CKE) == 0)
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freq = -freq;
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reg = anapllout_input[mux].reg;
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if(reg){
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int shift = anapllout_input[mux].shift;
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div = ((anatop[reg] >> shift) & 7)+1;
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} else {
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div = 1;
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}
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return freq / div;
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}
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static u32int
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clkgate(Clock *gate, u32int val)
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{
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@ -1330,6 +1414,11 @@ setclkrate(char *name, char *source, int freq)
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{
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int root, input;
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if(cistrcmp(name, "ccm_analog_pllout") == 0){
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setanapllout(lookinputclk(source), freq);
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return;
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}
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if((root = lookrootclk(name)) < 0)
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panic("setclkrate: clock %s not defined", name);
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if(source == nil)
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@ -1346,6 +1435,9 @@ getclkrate(char *name)
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{
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int root, input;
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if(cistrcmp(name, "ccm_analog_pllout") == 0)
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return getanapllout();
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if((root = lookrootclk(name)) >= 0)
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return rootclkgetcfg(root, &input);
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@ -159,3 +159,10 @@ extern uint iomuxgpr(int gpr, uint set, uint mask);
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#define GPIO_PIN(n, m) ((n)<<5 | (m))
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extern void gpioout(uint pin, int set);
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extern int gpioin(uint pin);
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/* pciimx */
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extern int pcicfgrw8(int tbdf, int rno, int data, int read);
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extern int pcicfgrw16(int tbdf, int rno, int data, int read);
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extern int pcicfgrw32(int tbdf, int rno, int data, int read);
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extern void pciintrenable(int tbdf, void (*f)(Ureg*, void*), void *a);
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extern void pciintrdisable(int tbdf, void (*f)(Ureg*, void*), void *a);
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@ -254,6 +254,11 @@ intrenable(int irq, void (*f)(Ureg*, void*), void *a, int tbdf, char *)
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u32int intid;
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int cpu, prio;
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if(BUSTYPE(tbdf) == BusPCI){
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pciintrenable(tbdf, f, a);
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return;
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}
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if(tbdf != BUSUNKNOWN)
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return;
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@ -306,6 +311,10 @@ intrenable(int irq, void (*f)(Ureg*, void*), void *a, int tbdf, char *)
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}
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void
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intrdisable(int, void (*)(Ureg*, void*), void *, int, char*)
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intrdisable(int tbdf, void (*f)(Ureg*, void*), void *a, int, char*)
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{
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if(BUSTYPE(tbdf) == BusPCI){
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pciintrdisable(tbdf, f, a);
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return;
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}
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}
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@ -28,7 +28,12 @@ enum {
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IRQsctr0 = SPI+47,
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IRQsctr1 = SPI+48,
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IRQpci2 = SPI+74,
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IRQenet1 = SPI+118,
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IRQpci1 = SPI+122,
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};
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#define BUSUNKNOWN (-1)
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#define PCIWADDR(x) PADDR(x)
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497
sys/src/9/imx8/pciimx.c
Normal file
497
sys/src/9/imx8/pciimx.c
Normal file
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@ -0,0 +1,497 @@
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/pci.h"
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typedef struct Intvec Intvec;
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struct Intvec
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{
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Pcidev *p;
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void (*f)(Ureg*, void*);
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void *a;
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};
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typedef struct Ctlr Ctlr;
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struct Ctlr
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{
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uvlong mem_base;
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uvlong mem_size;
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uvlong cfg_base;
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uvlong cfg_size;
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uvlong io_base;
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uvlong io_size;
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int bno, ubn;
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int irq;
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u32int *dbi;
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u32int *cfg;
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Pcidev *bridge;
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Lock;
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Intvec vec[32];
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};
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static Ctlr ctlrs[2] = {
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{
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0x18000000, 0x7f00000,
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0x1ff00000, 0x80000,
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0x1ff80000, 0x10000,
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0, 127, IRQpci1,
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(u32int*)(VIRTIO + 0x3800000),
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},
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{
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0x20000000, 0x7f00000,
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0x27f00000, 0x80000,
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0x27f80000, 0x10000,
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128, 255, IRQpci2,
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(u32int*)(VIRTIO + 0x3c00000),
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},
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};
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enum {
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IATU_MAX = 8,
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IATU_INBOUND = 1<<0,
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IATU_INDEX_SHIFT = 1,
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IATU_OFFSET = 0x300000/4,
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IATU_STRIDE = 0x100/4,
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IATU_REGION_CTRL_1 = 0x00/4,
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CTRL_1_FUNC_NUM_SHIFT = 20,
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CTRL_1_FUNC_NUM_MASK = 7<<CTRL_1_FUNC_NUM_SHIFT,
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CTRL_1_INCREASE_REGION_SIZ = 1<<13,
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CTRL_1_ATTR_SHIFT = 9,
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CTRL_1_ATTR_MASK = 3<<CTRL_1_ATTR_SHIFT,
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CTRL_1_TD = 1<<8,
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CTRL_1_TC_SHIFT = 5,
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CTRL_1_TC_MASK = 7<<CTRL_1_TC_SHIFT,
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CTRL_1_TYPE_SHIFT = 0,
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CTRL_1_TYPE_MASK = 0x1F<<CTRL_1_TYPE_SHIFT,
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CTRL_1_TYPE_MEM = 0x0<<CTRL_1_TYPE_SHIFT,
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CTRL_1_TYPE_IO = 0x2<<CTRL_1_TYPE_SHIFT,
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CTRL_1_TYPE_CFG0 = 0x4<<CTRL_1_TYPE_SHIFT,
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CTRL_1_TYPE_CFG1 = 0x5<<CTRL_1_TYPE_SHIFT,
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IATU_REGION_CTRL_2 = 0x04/4,
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CTRL_2_REGION_EN = 1<<31,
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CTRL_2_INVERT_MODE = 1<<29,
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CTRL_2_CFG_SHIFT_MODE = 1<<28,
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CTRL_2_DMA_BYPASS = 1<<27,
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CTRL_2_HEADER_SUBSITUTE_EN = 1<<23,
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CTRL_2_INHIBIT_PAYLOAD = 1<<22,
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CTRL_2_SNP = 1<<20,
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CTRL_2_FUNC_BYPASS = 1<<19,
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CTRL_2_TAG_SUBSTITUTE_EN = 1<<16,
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IATU_LWR_BSAE_ADDR = 0x08/4,
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IATU_UPPER_BASE_ADDR = 0x0C/4,
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IATU_LWR_LIMIT_ADDR = 0x10/4,
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IATU_LWR_TARGET_ADDR = 0x14/4,
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IATU_UPPER_TARGET_ADDR = 0x18/4,
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IATU_UPPER_LIMIT_ADDR = 0x20/4, /* undocumented */
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};
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/* disable all iATU's */
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static void
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iatuinit(Ctlr *ctlr)
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{
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u32int *reg;
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int index;
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for(index=0; index < IATU_MAX; index++){
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reg = &ctlr->dbi[IATU_OFFSET + IATU_STRIDE*index];
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reg[IATU_REGION_CTRL_2] &= ~CTRL_2_REGION_EN;
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}
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}
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static void
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iatucfg(Ctlr *ctlr, int index, u32int type, uvlong target, uvlong base, uvlong size)
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{
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uvlong limit = base + size - 1;
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u32int *reg;
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assert(size > 0);
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assert(index < IATU_MAX);
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assert((index & IATU_INBOUND) == 0);
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reg = &ctlr->dbi[IATU_OFFSET + IATU_STRIDE*index];
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reg[IATU_REGION_CTRL_2] &= ~CTRL_2_REGION_EN;
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reg[IATU_LWR_BSAE_ADDR] = base;
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reg[IATU_UPPER_BASE_ADDR] = base >> 32;
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reg[IATU_LWR_LIMIT_ADDR] = limit;
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reg[IATU_UPPER_LIMIT_ADDR] = limit >> 32;
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reg[IATU_LWR_TARGET_ADDR] = target;
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reg[IATU_UPPER_TARGET_ADDR] = target >> 32;
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type &= CTRL_1_TYPE_MASK;
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if(((size-1)>>32) != 0)
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type |= CTRL_1_INCREASE_REGION_SIZ;
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reg[IATU_REGION_CTRL_1] = type;
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reg[IATU_REGION_CTRL_2] = CTRL_2_REGION_EN;
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while((reg[IATU_REGION_CTRL_2] & CTRL_2_REGION_EN) == 0)
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microdelay(10);
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}
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static Ctlr*
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bus2ctlr(int bno)
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{
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Ctlr *ctlr;
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for(ctlr = ctlrs; ctlr < &ctlrs[nelem(ctlrs)]; ctlr++)
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if(bno >= ctlr->bno && bno <= ctlr->ubn)
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return ctlr;
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return nil;
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}
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static void*
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cfgaddr(int tbdf, int rno)
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{
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Ctlr *ctlr;
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ctlr = bus2ctlr(BUSBNO(tbdf));
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if(ctlr == nil)
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return nil;
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if(pciparentdev == nil){
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if(BUSDNO(tbdf) != 0 || BUSFNO(tbdf) != 0)
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return nil;
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return (uchar*)ctlr->dbi + rno;
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}
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iatucfg(ctlr, 0<<IATU_INDEX_SHIFT,
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pciparentdev->parent==nil? CTRL_1_TYPE_CFG0: CTRL_1_TYPE_CFG1,
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BUSBNO(tbdf)<<24 | BUSDNO(tbdf)<<19 | BUSFNO(tbdf)<<16,
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ctlr->cfg_base, ctlr->cfg_size);
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return (uchar*)ctlr->cfg + rno;
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}
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int
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pcicfgrw32(int tbdf, int rno, int data, int read)
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{
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u32int *p;
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if((p = cfgaddr(tbdf, rno & ~3)) != nil){
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if(read)
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data = *p;
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else
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*p = data;
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} else {
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data = -1;
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}
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return data;
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}
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int
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pcicfgrw16(int tbdf, int rno, int data, int read)
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{
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u16int *p;
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if((p = cfgaddr(tbdf, rno & ~1)) != nil){
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if(read)
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data = *p;
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else
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*p = data;
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} else {
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data = -1;
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}
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return data;
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}
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int
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pcicfgrw8(int tbdf, int rno, int data, int read)
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{
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u8int *p;
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if((p = cfgaddr(tbdf, rno)) != nil){
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if(read)
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data = *p;
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else
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*p = data;
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} else {
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data = -1;
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}
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return data;
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}
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static u16int msimsg;
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#define MSI_TARGET_ADDR PADDR(&msimsg)
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enum {
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MSI_CAP_ID = 0x50/4,
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PCI_MSI_ENABLE = 1<<16,
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MSI_CTRL_ADDR = 0x820/4,
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MSI_CTRL_UPPER_ADDR = 0x824/4,
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MSI_CTRL_INT_0_EN = 0x828/4,
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MSI_CTRL_INT_0_MASK = 0x82C/4,
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MSI_CTRL_INT_0_STATUS = 0x830/4,
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MISC_CONTROL_1 = 0x8BC/4,
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DBI_RO_WR_EN = 1<<0,
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};
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static void
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pciinterrupt(Ureg *ureg, void *arg)
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{
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Ctlr *ctlr = arg;
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Intvec *vec;
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u32int status, mask;
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status = ctlr->dbi[MSI_CTRL_INT_0_STATUS];
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if(status == 0)
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return;
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ctlr->dbi[MSI_CTRL_INT_0_STATUS] = status;
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ilock(ctlr);
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for(vec = ctlr->vec, mask = 1; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++, mask <<= 1){
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if((status & mask) != 0 && vec->f != nil)
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(*vec->f)(ureg, vec->a);
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}
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iunlock(ctlr);
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}
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static void
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pciintrinit(Ctlr *ctlr)
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{
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ctlr->dbi[MSI_CTRL_INT_0_EN] = 0;
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ctlr->dbi[MSI_CTRL_INT_0_MASK] = 0;
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ctlr->dbi[MSI_CTRL_INT_0_STATUS] = -1;
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ctlr->dbi[MSI_CTRL_ADDR] = MSI_TARGET_ADDR;
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ctlr->dbi[MSI_CTRL_UPPER_ADDR] = MSI_TARGET_ADDR >> 32;
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intrenable(ctlr->irq+0, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
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intrenable(ctlr->irq+1, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
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intrenable(ctlr->irq+2, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
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intrenable(ctlr->irq+3, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
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ctlr->dbi[MSI_CAP_ID] |= PCI_MSI_ENABLE;
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}
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void
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pciintrenable(int tbdf, void (*f)(Ureg*, void*), void *a)
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{
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Ctlr *ctlr;
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Intvec *vec;
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Pcidev *p;
|
||||
|
||||
ctlr = bus2ctlr(BUSBNO(tbdf));
|
||||
if(ctlr == nil){
|
||||
print("pciintrenable: %T: unknown controller\n", tbdf);
|
||||
return;
|
||||
}
|
||||
|
||||
if((p = pcimatchtbdf(tbdf)) == nil){
|
||||
print("pciintrenable: %T: unknown device\n", tbdf);
|
||||
return;
|
||||
}
|
||||
if(pcimsidisable(p) < 0){
|
||||
print("pciintrenable: %T: device doesnt support vec\n", tbdf);
|
||||
return;
|
||||
}
|
||||
|
||||
ilock(ctlr);
|
||||
for(vec = ctlr->vec; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++){
|
||||
if(vec->p == p){
|
||||
ctlr->dbi[MSI_CTRL_INT_0_EN] &= ~(1 << (vec - ctlr->vec));
|
||||
vec->p = nil;
|
||||
break;
|
||||
}
|
||||
}
|
||||
for(vec = ctlr->vec; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++){
|
||||
if(vec->p == nil){
|
||||
vec->p = p;
|
||||
vec->a = a;
|
||||
vec->f = f;
|
||||
break;
|
||||
}
|
||||
}
|
||||
iunlock(ctlr);
|
||||
|
||||
if(vec >= &ctlr->vec[nelem(ctlr->vec)]){
|
||||
print("pciintrenable: %T: out of isr slots\n", tbdf);
|
||||
return;
|
||||
}
|
||||
ctlr->dbi[MSI_CTRL_INT_0_EN] |= (1 << (vec - ctlr->vec));
|
||||
pcimsienable(p, MSI_TARGET_ADDR, vec - ctlr->vec);
|
||||
}
|
||||
|
||||
void
|
||||
pciintrdisable(int tbdf, void (*f)(Ureg*, void*), void *a)
|
||||
{
|
||||
Ctlr *ctlr;
|
||||
Intvec *vec;
|
||||
|
||||
ctlr = bus2ctlr(BUSBNO(tbdf));
|
||||
if(ctlr == nil){
|
||||
print("pciintrenable: %T: unknown controller\n", tbdf);
|
||||
return;
|
||||
}
|
||||
|
||||
ilock(ctlr);
|
||||
for(vec = ctlr->vec; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++){
|
||||
if(vec->p == nil)
|
||||
continue;
|
||||
if(vec->p->tbdf == tbdf && vec->f == f && vec->a == a){
|
||||
ctlr->dbi[MSI_CTRL_INT_0_EN] &= ~(1 << (vec - ctlr->vec));
|
||||
vec->f = nil;
|
||||
vec->a = nil;
|
||||
vec->p = nil;
|
||||
break;
|
||||
}
|
||||
}
|
||||
iunlock(ctlr);
|
||||
}
|
||||
|
||||
static void
|
||||
rootinit(Ctlr *ctlr)
|
||||
{
|
||||
uvlong base;
|
||||
ulong ioa;
|
||||
|
||||
iatuinit(ctlr);
|
||||
|
||||
ctlr->cfg = vmap(ctlr->cfg_base, ctlr->cfg_size);
|
||||
if(ctlr->cfg == nil)
|
||||
return;
|
||||
|
||||
ctlr->dbi[MISC_CONTROL_1] |= DBI_RO_WR_EN;
|
||||
|
||||
/* bus number */
|
||||
ctlr->dbi[PciPBN/4] &= ~0xFFFFFF;
|
||||
ctlr->dbi[PciPBN/4] |= ctlr->bno | (ctlr->bno+1)<<8 | ctlr->ubn<<16;
|
||||
|
||||
/* command */
|
||||
ctlr->dbi[PciPCR/4] &= ~0xFFFF;
|
||||
ctlr->dbi[PciPCR/4] |= IOen | MEMen | MASen | SErrEn;
|
||||
|
||||
/* device class/subclass */
|
||||
ctlr->dbi[PciRID/4] &= ~0xFFFF0000;
|
||||
ctlr->dbi[PciRID/4] |= 0x06040000;
|
||||
|
||||
ctlr->dbi[PciBAR0/4] = 0;
|
||||
ctlr->dbi[PciBAR1/4] = 0;
|
||||
|
||||
ctlr->dbi[MISC_CONTROL_1] &= ~DBI_RO_WR_EN;
|
||||
|
||||
ctlr->ubn = pciscan(ctlr->bno, &ctlr->bridge, nil);
|
||||
if(ctlr->bridge == nil || ctlr->bridge->bridge == nil)
|
||||
return;
|
||||
|
||||
pciintrinit(ctlr);
|
||||
|
||||
iatucfg(ctlr, 1<<IATU_INDEX_SHIFT, CTRL_1_TYPE_IO, ctlr->io_base, ctlr->io_base, ctlr->io_size);
|
||||
iatucfg(ctlr, 2<<IATU_INDEX_SHIFT, CTRL_1_TYPE_MEM, ctlr->mem_base, ctlr->mem_base, ctlr->mem_size);
|
||||
|
||||
ioa = ctlr->io_base;
|
||||
base = ctlr->mem_base;
|
||||
pcibusmap(ctlr->bridge, &base, &ioa, 1);
|
||||
|
||||
pcihinv(ctlr->bridge);
|
||||
}
|
||||
|
||||
static void
|
||||
pcicfginit(void)
|
||||
{
|
||||
fmtinstall('T', tbdffmt);
|
||||
rootinit(&ctlrs[0]);
|
||||
rootinit(&ctlrs[1]);
|
||||
}
|
||||
|
||||
enum {
|
||||
SRC_PCIEPHY_RCR = 0x2C/4,
|
||||
SRC_PCIE2_RCR = 0x48/4,
|
||||
PCIE_CTRL_APP_XFER_PENDING = 1<<16,
|
||||
PCIE_CTRL_APP_UNLOCK_MSG = 1<<15,
|
||||
PCIE_CTRL_SYS_INT = 1<<14,
|
||||
PCIE_CTRL_CFG_L1_AUX = 1<<12,
|
||||
PCIE_CTRL_APPS_TURNOFF = 1<<11,
|
||||
PCIE_CTRL_APPS_PME = 1<<10,
|
||||
PCIE_CTRL_APPS_EXIT = 1<<9,
|
||||
PCIE_CTRL_APPS_ENTER = 1<<8,
|
||||
PCIE_CTRL_APPS_READY = 1<<7,
|
||||
PCIE_CTRL_APPS_EN = 1<<6,
|
||||
PCIE_CTRL_APPS_RST = 1<<5,
|
||||
PCIE_CTRL_APPS_CLK_REQ = 1<<4,
|
||||
PCIE_PERST = 1<<3,
|
||||
PCIE_BTN = 1<<2,
|
||||
PCIE_G_RST = 1<<1,
|
||||
PCIE_PHY_POWER_ON_RESET_N = 1<<0,
|
||||
};
|
||||
|
||||
static u32int *resetc = (u32int*)(VIRTIO + 0x390000);
|
||||
|
||||
void
|
||||
pciimxlink(void)
|
||||
{
|
||||
resetc[SRC_PCIEPHY_RCR] |= PCIE_BTN | PCIE_G_RST;
|
||||
resetc[SRC_PCIE2_RCR] |= PCIE_BTN | PCIE_G_RST;
|
||||
|
||||
resetc[SRC_PCIEPHY_RCR] |= PCIE_CTRL_APPS_EN;
|
||||
resetc[SRC_PCIE2_RCR] |= PCIE_CTRL_APPS_EN;
|
||||
|
||||
setclkgate("pcie_clk_rst.auxclk", 0);
|
||||
setclkgate("pcie2_clk_rst.auxclk", 0);
|
||||
|
||||
iomuxpad("pad_ecspi1_mosi", "gpio5_io07", "~LVTTL ~HYS ~PUE ~ODE FAST 45_OHM");
|
||||
iomuxpad("pad_sai5_rxd2", "gpio3_io23", "~LVTTL ~HYS ~PUE ~ODE FAST 45_OHM");
|
||||
|
||||
gpioout(GPIO_PIN(5, 7), 0);
|
||||
gpioout(GPIO_PIN(3, 23), 0);
|
||||
|
||||
powerup("pcie");
|
||||
powerup("pcie2");
|
||||
|
||||
/* configure monitor CLK2 output internal reference clock for PCIE1 */
|
||||
setclkrate("ccm_analog_pllout", "system_pll1_clk", 100*Mhz);
|
||||
delay(10);
|
||||
|
||||
/* PCIE1_REF_USE_PAD=0 */
|
||||
iomuxgpr(14, 0<<9, 1<<9);
|
||||
|
||||
/* PCIE2_REF_USE_PAD=1 */
|
||||
iomuxgpr(16, 1<<9, 1<<9);
|
||||
|
||||
/* PCIE1_CTRL_DEVICE_TYPE=ROOT, PCIE2_CTRL_DEVICE_TYPE=ROOT */
|
||||
iomuxgpr(12, 4<<12 | 4<<8, 0xF<<12 | 0xF<<8);
|
||||
|
||||
setclkrate("ccm_pcie1_ctrl_clk_root", "system_pll2_div4", 250*Mhz);
|
||||
setclkrate("ccm_pcie2_ctrl_clk_root", "system_pll2_div4", 250*Mhz);
|
||||
|
||||
setclkrate("pcie_clk_rst.auxclk", "system_pll2_div10", 100*Mhz);
|
||||
setclkrate("pcie2_clk_rst.auxclk", "system_pll2_div10", 100*Mhz);
|
||||
|
||||
setclkrate("pcie_phy.ref_alt_clk_p", "system_pll2_div10", 100*Mhz);
|
||||
setclkrate("pcie2_phy.ref_alt_clk_p", "system_pll2_div10", 100*Mhz);
|
||||
|
||||
setclkgate("pcie_clk_rst.auxclk", 1);
|
||||
setclkgate("pcie2_clk_rst.auxclk", 1);
|
||||
|
||||
/* PCIE1_CLKREQ_B_OVERRIDE=0 PCIE1_CLKREQ_B_OVERRIDE_EN=1 */
|
||||
iomuxgpr(14, 1<<10, 3<<10);
|
||||
|
||||
/* PCIE2_CLKREQ_B_OVERRIDE=0 PCIE2_CLKREQ_B_OVERRIDE_EN=1 */
|
||||
iomuxgpr(16, 1<<10, 3<<10);
|
||||
|
||||
delay(100);
|
||||
gpioout(GPIO_PIN(5, 7), 1);
|
||||
gpioout(GPIO_PIN(3, 23), 1);
|
||||
delay(1);
|
||||
|
||||
resetc[SRC_PCIEPHY_RCR] &= ~(PCIE_BTN | PCIE_G_RST);
|
||||
resetc[SRC_PCIE2_RCR] &= ~(PCIE_BTN | PCIE_G_RST);
|
||||
|
||||
pcicfginit();
|
||||
}
|
||||
|
|
@ -27,6 +27,7 @@ link
|
|||
ethermedium
|
||||
loopbackmedium
|
||||
i2cimx devi2c
|
||||
pciimx pci
|
||||
ip
|
||||
tcp
|
||||
udp
|
||||
|
|
@ -44,6 +45,7 @@ misc
|
|||
uartimx
|
||||
iomux
|
||||
sdmmc usdhc
|
||||
sdnvme pci
|
||||
port
|
||||
int cpuserver = 0;
|
||||
bootdir
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ struct Pcisiz
|
|||
};
|
||||
|
||||
int pcimaxdno;
|
||||
Pcidev *pciparentdev;
|
||||
|
||||
static Lock pcicfglock;
|
||||
static Pcidev *pcilist, **pcitail;
|
||||
|
|
@ -113,6 +114,8 @@ pcicfgr8(Pcidev* p, int rno)
|
|||
int data;
|
||||
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
data = pcicfgrw8(p->tbdf, rno, 0, 1);
|
||||
iunlock(&pcicfglock);
|
||||
|
||||
|
|
@ -122,6 +125,8 @@ void
|
|||
pcicfgw8(Pcidev* p, int rno, int data)
|
||||
{
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
pcicfgrw8(p->tbdf, rno, data, 0);
|
||||
iunlock(&pcicfglock);
|
||||
}
|
||||
|
|
@ -131,6 +136,8 @@ pcicfgr16(Pcidev* p, int rno)
|
|||
int data;
|
||||
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
data = pcicfgrw16(p->tbdf, rno, 0, 1);
|
||||
iunlock(&pcicfglock);
|
||||
|
||||
|
|
@ -140,6 +147,8 @@ void
|
|||
pcicfgw16(Pcidev* p, int rno, int data)
|
||||
{
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
pcicfgrw16(p->tbdf, rno, data, 0);
|
||||
iunlock(&pcicfglock);
|
||||
}
|
||||
|
|
@ -149,6 +158,8 @@ pcicfgr32(Pcidev* p, int rno)
|
|||
int data;
|
||||
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
data = pcicfgrw32(p->tbdf, rno, 0, 1);
|
||||
iunlock(&pcicfglock);
|
||||
|
||||
|
|
@ -158,6 +169,8 @@ void
|
|||
pcicfgw32(Pcidev* p, int rno, int data)
|
||||
{
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
pcicfgrw32(p->tbdf, rno, data, 0);
|
||||
iunlock(&pcicfglock);
|
||||
}
|
||||
|
|
@ -169,6 +182,7 @@ pcibarsize(Pcidev *p, int rno)
|
|||
int v;
|
||||
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
v = pcicfgrw32(p->tbdf, rno, 0, 1);
|
||||
pcicfgrw32(p->tbdf, rno, -1, 0);
|
||||
|
|
@ -206,6 +220,8 @@ void
|
|||
pcisetbar(Pcidev *p, int rno, uvlong bar)
|
||||
{
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
pcicfgrw32(p->tbdf, rno, bar, 0);
|
||||
if((bar&7) == 4 && rno >= PciBAR0 && rno < PciBAR0+4*(nelem(p->mem)-1))
|
||||
pcicfgrw32(p->tbdf, rno+4, bar>>32, 0);
|
||||
|
|
@ -216,6 +232,8 @@ void
|
|||
pcisetwin(Pcidev *p, uvlong base, uvlong limit)
|
||||
{
|
||||
ilock(&pcicfglock);
|
||||
pciparentdev = p->parent;
|
||||
|
||||
if(base & 1){
|
||||
pcicfgrw16(p->tbdf, PciIBR, (limit & 0xF000)|((base & 0xF000)>>8), 0);
|
||||
pcicfgrw32(p->tbdf, PciIUBR, (limit & 0xFFFF0000)|(base>>16), 0);
|
||||
|
|
@ -534,12 +552,15 @@ pciscan(int bno, Pcidev** list, Pcidev *parent)
|
|||
tbdf = MKBUS(BusPCI, bno, dno, fno);
|
||||
|
||||
lock(&pcicfglock);
|
||||
pciparentdev = parent;
|
||||
|
||||
l = pcicfgrw32(tbdf, PciVID, 0, 1);
|
||||
unlock(&pcicfglock);
|
||||
|
||||
if(l == 0xFFFFFFFF || l == 0)
|
||||
continue;
|
||||
p = pcidevalloc();
|
||||
p->parent = parent;
|
||||
p->tbdf = tbdf;
|
||||
p->vid = l;
|
||||
p->did = l>>16;
|
||||
|
|
@ -622,7 +643,6 @@ pciscan(int bno, Pcidev** list, Pcidev *parent)
|
|||
break;
|
||||
}
|
||||
|
||||
p->parent = parent;
|
||||
if(head != nil)
|
||||
*tail = p;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -223,6 +223,7 @@ enum
|
|||
};
|
||||
|
||||
extern int pcimaxdno;
|
||||
extern Pcidev *pciparentdev;
|
||||
|
||||
extern void pcidevfree(Pcidev* pcidev);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue