vga/igfx: work in progress fdi link train for sandy bridge, properly calculate fdi and displayport lane count
This commit is contained in:
cinap_lenrek
parent
713beb6d42
commit
540373b9f6
1 changed files with 94 additions and 31 deletions
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@ -89,6 +89,8 @@ struct Fdi {
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Reg rxctl; /* FDI_RX_CTL */
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Reg rxmisc; /* FDI_RX_MISC */
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Reg rxiir; /* FDI_RX_IIR */
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Reg rximr; /* FDI_RX_IMR */
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Reg rxtu[2]; /* FDI_RX_TUSIZE */
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};
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@ -276,6 +278,10 @@ snarfpipe(Igfx *igfx, int x)
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p->fdi->rxctl = snarfreg(igfx, o + 0x1000c);
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p->fdi->rxmisc = snarfreg(igfx, o + 0x10010);
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p->fdi->rxiir = snarfreg(igfx, o + 0x10014);
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p->fdi->rximr = snarfreg(igfx, o + 0x10018);
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p->fdi->rxtu[0] = snarfreg(igfx, o + 0x10030);
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p->fdi->rxtu[1] = snarfreg(igfx, o + 0x10038);
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@ -297,7 +303,6 @@ snarfpipe(Igfx *igfx, int x)
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/* cursor plane */
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switch(igfx->type){
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case TypeIVB:
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case TypeSNB:
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p->cur->cntr = snarfreg(igfx, 0x70080 + x*0x1000);
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p->cur->base = snarfreg(igfx, 0x70084 + x*0x1000);
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p->cur->pos = snarfreg(igfx, 0x70088 + x*0x1000);
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@ -305,7 +310,8 @@ snarfpipe(Igfx *igfx, int x)
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case TypeG45:
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p->dsp->pos = snarfreg(igfx, 0x7018C + x*0x1000);
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p->dsp->size = snarfreg(igfx, 0x70190 + x*0x1000);
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/* wet floor */
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case TypeSNB:
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p->cur->cntr = snarfreg(igfx, 0x70080 + x*0x40);
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p->cur->base = snarfreg(igfx, 0x70084 + x*0x40);
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p->cur->pos = snarfreg(igfx, 0x70088 + x*0x40);
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@ -320,10 +326,13 @@ devtype(Igfx *igfx)
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return -1;
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switch(igfx->pci->did){
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case 0x0166: /* 3rd Gen Core - ThinkPad X230 */
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case 0x0152: /* 2nd/3rd Gen Core - Core-i3 */
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return TypeIVB;
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case 0x0102: /* Dell Optiplex 790 */
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case 0x0126: /* Thinkpad X220 */
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return TypeSNB;
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case 0x27a2: /* GM945/82940GML - ThinkPad X60 Tablet */
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case 0x29a2: /* 82P965/G965 HECI desktop */
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case 0x2a02: /* GM965/GL960/X3100 - ThinkPad X61 Tablet */
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case 0x2a42: /* 4 Series Mobile - ThinkPad X200 */
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return TypeG45;
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@ -689,6 +698,18 @@ initdpll(Igfx *igfx, int x, int freq, int port)
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return 0;
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}
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static int
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needlanes(int freq, int lsclk, int bpp)
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{
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vlong v;
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int n;
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v = ((vlong)freq * bpp) / 8;
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for(n=1; n<4 && v>lsclk; n<<=1, v>>=1)
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;
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return n;
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}
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static void
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initdatalinkmn(Trans *t, int freq, int lsclk, int lanes, int tu, int bpp)
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{
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@ -734,10 +755,10 @@ inittrans(Trans *t, Mode *m)
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}
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static void
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initpipe(Pipe *p, Mode *m)
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initpipe(Pipe *p, Mode *m, int bpc)
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{
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static uchar bpctab[4] = { 8, 10, 6, 12 };
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int i, tu, bpc, lanes;
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int i, tu, lanes;
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Fdi *fdi;
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/* source image size */
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@ -754,9 +775,8 @@ initpipe(Pipe *p, Mode *m)
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inittrans(p, m);
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/* default for displayport */
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lanes = needlanes(m->frequency, 270*MHz, 3*bpc);
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tu = 64;
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bpc = 6; /* why */
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lanes = 1;
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fdi = p->fdi;
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if(fdi->rxctl.a != 0){
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@ -805,7 +825,7 @@ initpipe(Pipe *p, Mode *m)
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static void
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init(Vga* vga, Ctlr* ctlr)
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{
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int x, port;
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int x, port, bpc;
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char *val;
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Igfx *igfx;
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Pipe *p;
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@ -816,6 +836,8 @@ init(Vga* vga, Ctlr* ctlr)
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if(m->z != 32)
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error("%s: unsupported color depth %d\n", ctlr->name, m->z);
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bpc = 8; /* bits per color channel */
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igfx = vga->private;
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/* disable vga */
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@ -858,10 +880,10 @@ init(Vga* vga, Ctlr* ctlr)
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break;
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case PortVGA:
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if(igfx->npipe > 2)
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x = (igfx->adpa.v >> 29) & 3;
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else
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if(igfx->type == TypeG45)
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x = (igfx->adpa.v >> 30) & 1;
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else
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x = (igfx->adpa.v >> 29) & 3;
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igfx->adpa.v |= (1<<31);
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if(igfx->type == TypeG45){
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igfx->adpa.v &= ~(3<<10); /* Monitor DPMS: on */
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@ -876,10 +898,10 @@ init(Vga* vga, Ctlr* ctlr)
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break;
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case PortLCD:
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if(igfx->npipe > 2)
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x = (igfx->lvds.v >> 29) & 3;
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else
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if(igfx->type == TypeG45)
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x = (igfx->lvds.v >> 30) & 1;
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else
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x = (igfx->lvds.v >> 29) & 3;
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igfx->lvds.v |= (1<<31);
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igfx->ppcontrol.v |= 5;
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@ -905,8 +927,9 @@ init(Vga* vga, Ctlr* ctlr)
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goto Badport;
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/* port enable */
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r->v |= 1<<31;
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/* port width selection: x1 Mode */
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/* port width selection */
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r->v &= ~(7<<19);
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r->v |= needlanes(m->frequency, 270*MHz, 3*bpc)-1 << 19;
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/* port reversal: off */
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r->v &= ~(1<<15);
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@ -975,7 +998,7 @@ init(Vga* vga, Ctlr* ctlr)
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if(initdpll(igfx, x, m->frequency, port) < 0)
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error("%s: frequency %d out of range\n", ctlr->name, m->frequency);
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initpipe(p, m);
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initpipe(p, m, bpc);
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ctlr->flag |= Finit;
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}
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@ -1053,8 +1076,8 @@ enablepipe(Igfx *igfx, int x)
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loadreg(igfx, p->fdi->rxctl);
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sleep(5);
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p->fdi->txctl.v &= ~(7<<8 | 1); /* clear auto training bits */
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p->fdi->txctl.v &= ~(1<<31);
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p->fdi->rxctl.v |= (1<<14); /* enable pll */
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p->fdi->txctl.v &= ~(1<<31); /* disable */
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p->fdi->txctl.v |= (1<<14); /* enable pll */
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loadreg(igfx, p->fdi->txctl);
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sleep(5);
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}
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@ -1102,21 +1125,61 @@ enablepipe(Igfx *igfx, int x)
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loadreg(igfx, p->fdi->rxtu[0]);
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loadreg(igfx, p->fdi->rxmisc);
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p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 00 */
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p->fdi->rxctl.v |= 1<<10; /* auto train enable */
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p->fdi->rxctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->rxctl);
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if(igfx->type == TypeSNB){
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/* unmask bit lock and symbol lock bits */
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csr(igfx, p->fdi->rximr.a, 3<<8, 0);
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p->fdi->txctl.v &= ~(3<<8); /* link train pattern 00 */
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p->fdi->txctl.v |= 1<<10; /* auto train enable */
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p->fdi->txctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->txctl);
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p->fdi->rxctl.v &= ~(3<<8); /* link train pattern1 */
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p->fdi->rxctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->rxctl);
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/* wait for link training done */
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for(i=0; i<200; i++){
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p->fdi->txctl.v &= ~(3<<8); /* link train pattern1 */
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p->fdi->txctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->txctl);
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/* wait for bit lock */
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for(i=0; i<10; i++){
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sleep(1);
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if(rr(igfx, p->fdi->rxiir.a) & (1<<8))
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break;
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}
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csr(igfx, p->fdi->rxiir.a, 0, 1<<8);
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/* switch to link train pattern2 */
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csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
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csr(igfx, p->fdi->txctl.a, 3<<8, 1<<8);
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/* wait for symbol lock */
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for(i=0; i<10; i++){
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sleep(1);
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if(rr(igfx, p->fdi->rxiir.a) & (1<<9))
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break;
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}
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csr(igfx, p->fdi->rxiir.a, 0, 1<<9);
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/* switch to link train normal */
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csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
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csr(igfx, p->fdi->txctl.a, 0, 3<<8);
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/* wait idle pattern time */
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sleep(5);
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if(rr(igfx, p->fdi->txctl.a) & 2)
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break;
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} else {
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p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 00 */
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p->fdi->rxctl.v |= 1<<10; /* auto train enable */
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p->fdi->rxctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->rxctl);
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p->fdi->txctl.v &= ~(3<<8); /* link train pattern 00 */
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p->fdi->txctl.v |= 1<<10; /* auto train enable */
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p->fdi->txctl.v |= 1<<31; /* enable */
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loadreg(igfx, p->fdi->txctl);
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/* wait for link training done */
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for(i=0; i<200; i++){
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sleep(5);
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if(rr(igfx, p->fdi->txctl.a) & 2)
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break;
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}
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}
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}
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@ -1626,8 +1689,8 @@ enabledp(Igfx *igfx, Dp *dp)
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return 0;
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/* Link configuration */
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wdpaux(igfx, dp, 0x100, 0x0A); /* 270Mhz */
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wdpaux(igfx, dp, 0x101, 0x01); /* one lane */
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wdpaux(igfx, dp, 0x100, (270*MHz) / 27000000);
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wdpaux(igfx, dp, 0x101, ((dp->ctl.v>>19)&7)+1);
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r = 0;
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