pc, pc64: cleanup devarch
- shorten cpuidprnt so it doesnt have to break line - addarchfile: complain when running out of entries - fix range check in rmemrw() (harmless) - use nil instead of 0 for pointers
This commit is contained in:
cinap_lenrek
parent
35df6c32a2
commit
476a47b15c
1 changed files with 24 additions and 37 deletions
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@ -91,6 +91,7 @@ addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
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lock(&archwlock);
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if(narchdir >= Qmax){
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unlock(&archwlock);
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print("addarchfile: out of entries for %s\n", name);
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return nil;
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}
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@ -218,8 +219,7 @@ ioalloc(int port, int size, int align, char *tag)
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if(port < 0){
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/* find a free port above 0x400 and below 0x1000 */
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port = 0x400;
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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for(l = &iomap.m; (m = *l) != nil; l = &m->next){
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if (m->start < 0x400) continue;
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i = m->start - port;
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if(i > size)
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@ -229,7 +229,7 @@ ioalloc(int port, int size, int align, char *tag)
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else
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port = m->end;
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}
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if(*l == nil){
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if(m == nil){
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unlock(&iomap);
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return -1;
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}
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@ -240,8 +240,7 @@ ioalloc(int port, int size, int align, char *tag)
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return -1;
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}
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/* see if the space clashes with previously allocated ports */
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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for(l = &iomap.m; (m = *l) != nil; l = &m->next){
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if(m->end <= port)
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continue;
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if(m->reserved && m->start == port && m->end >= port + size) {
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@ -281,15 +280,14 @@ iofree(int port)
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IOMap *m, **l;
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lock(&iomap);
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for(l = &iomap.m; *l; l = &(*l)->next){
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if((*l)->start == port){
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m = *l;
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for(l = &iomap.m; (m = *l) != nil; l = &m->next){
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if(m->start == port){
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*l = m->next;
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m->next = iomap.free;
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iomap.free = m;
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break;
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}
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if((*l)->start > port)
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if(m->start > port)
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break;
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}
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archdir[0].qid.vers++;
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@ -301,7 +299,7 @@ iounused(int start, int end)
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{
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IOMap *m;
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for(m = iomap.m; m; m = m->next){
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for(m = iomap.m; m != nil; m = m->next){
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if(start >= m->start && start < m->end
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|| start <= m->start && end > m->start)
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return 0;
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@ -369,7 +367,6 @@ archread(Chan *c, void *a, long n, vlong offset)
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Rdwrfn *fn;
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switch((ulong)c->qid.path){
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case Qdir:
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return devdirread(c, a, n, archdir, narchdir, devgen);
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@ -451,7 +448,6 @@ archwrite(Chan *c, void *a, long n, vlong offset)
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Rdwrfn *fn;
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switch((ulong)c->qid.path){
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case Qiob:
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p = a;
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checkport(offset, offset+n);
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@ -487,7 +483,7 @@ archwrite(Chan *c, void *a, long n, vlong offset)
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return n;
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default:
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if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
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if(c->qid.path < narchdir && (fn = writefn[c->qid.path]) != nil)
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return fn(c, a, n, offset);
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error(Eperm);
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break;
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@ -731,16 +727,9 @@ simplecycles(uvlong*x)
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void
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cpuidprint(void)
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{
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int i;
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char buf[128];
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i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
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if(m->cpuidid[0])
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i += sprint(buf+i, "%12.12s ", m->cpuidid);
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seprint(buf+i, buf + sizeof buf - 1,
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"%s (cpuid: AX 0x%4.4uX CX 0x%4.4uX DX 0x%4.4uX)\n",
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m->cpuidtype, m->cpuidax, m->cpuidcx, m->cpuiddx);
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print(buf);
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print("cpu%d: %dMHz %s %s (AX %8.8uX CX %8.8uX DX %8.8uX)\n",
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m->machno, m->cpumhz, m->cpuidid, m->cpuidtype,
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m->cpuidax, m->cpuidcx, m->cpuiddx);
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}
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/*
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@ -964,7 +953,7 @@ static Cmdtab archctlmsg[] =
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CMpge, "pge", 2,
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CMcoherence, "coherence", 2,
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CMi8253set, "i8253set", 2,
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CMcache, "cache", 4,
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CMcache, "cache", 4,
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};
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static long
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@ -1047,7 +1036,7 @@ rmemrw(int isr, void *a, long n, vlong off)
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if(isr){
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if(addr >= MB)
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return 0;
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if(addr+n >= MB)
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if(addr+n > MB)
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n = MB - addr;
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memmove(a, KADDR(addr), n);
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}else{
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@ -1077,27 +1066,25 @@ archinit(void)
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{
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PCArch **p;
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arch = 0;
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for(p = knownarch; *p; p++){
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if((*p)->ident && (*p)->ident() == 0){
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arch = &archgeneric;
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for(p = knownarch; *p != nil; p++){
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if((*p)->ident != nil && (*p)->ident() == 0){
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arch = *p;
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break;
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}
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}
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if(arch == 0)
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arch = &archgeneric;
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else{
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if(arch->id == 0)
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if(arch != &archgeneric){
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if(arch->id == nil)
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arch->id = archgeneric.id;
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if(arch->reset == 0)
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if(arch->reset == nil)
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arch->reset = archgeneric.reset;
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if(arch->serialpower == 0)
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if(arch->serialpower == nil)
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arch->serialpower = archgeneric.serialpower;
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if(arch->modempower == 0)
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if(arch->modempower == nil)
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arch->modempower = archgeneric.modempower;
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if(arch->intrinit == 0)
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if(arch->intrinit == nil)
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arch->intrinit = archgeneric.intrinit;
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if(arch->intrenable == 0)
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if(arch->intrenable == nil)
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arch->intrenable = archgeneric.intrenable;
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}
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