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omap: update omap kernel (from sources)

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refactors of the usb ehci code and adds vfp support
This commit is contained in:
cinap_lenrek 2013-01-26 17:32:08 +01:00
parent 44eb643cb2
commit 43e09c468b
4 changed files with 166 additions and 154 deletions
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1
sys/src/9/omap/archomap.c
View file

@ -18,6 +18,7 @@
#include "etherif.h"
#include "../port/flashif.h"
#include "../port/usb.h"
#include "../port/portusbehci.h"
#include "usbehci.h"
#define FREQSEL(x) ((x) << 4)

26
sys/src/9/omap/trap.c
View file

@ -390,7 +390,7 @@ irq(Ureg* ureg)
switch (irqno) {
case 56:
case 57:
iprint(" (I²C)");
iprint(" (I⁲C)");
break;
case 83:
case 86:
@ -589,16 +589,22 @@ trap(Ureg *ureg)
break;
case PsrMund: /* undefined instruction */
if(user){
/* look for floating point instructions to interpret */
x = spllo();
rv = fpiarm(ureg);
splx(x);
if(rv == 0){
ldrexvalid = 0;
snprint(buf, sizeof buf,
"undefined instruction: pc %#lux\n",
ureg->pc);
if(seg(up, ureg->pc, 0) != nil &&
*(u32int*)ureg->pc == 0xD1200070){
snprint(buf, sizeof buf, "sys: breakpoint");
postnote(up, 1, buf, NDebug);
}else{
/* look for floating point instructions to interpret */
x = spllo();
rv = fpiarm(ureg);
splx(x);
if(rv == 0){
ldrexvalid = 0;
snprint(buf, sizeof buf,
"undefined instruction: pc %#lux\n",
ureg->pc);
postnote(up, 1, buf, NDebug);
}
}
}else{
if (ureg->pc & 3) {

149
sys/src/9/omap/usbehci.h
View file

@ -9,154 +9,19 @@
#define ddeprint if(ehcidebug>1 || ep->debug>1)print
typedef struct Ctlr Ctlr;
typedef struct Ecapio Ecapio;
typedef struct Eopio Eopio;
typedef struct Edbgio Edbgio;
typedef struct Isoio Isoio;
typedef struct Poll Poll;
typedef struct Qh Qh;
typedef struct Qtree Qtree;
#pragma incomplete Ctlr;
#pragma incomplete Ecapio;
#pragma incomplete Eopio;
#pragma incomplete Edbgio;
#pragma incomplete Isoio;
#pragma incomplete Poll;
#pragma incomplete Qh;
#pragma incomplete Qtree;
/*
* EHCI interface registers and bits
*/
enum
{
Cnports = 0xF, /* nport bits in Ecapio parms. */
Cdbgportshift = 20, /* debug port in Ecapio parms. */
Cdbgportmask = 0xF,
C64 = 1, /* 64-bits, in Ecapio capparms. */
Ceecpshift = 8, /* extended capabilities ptr. in */
Ceecpmask = 8, /* the Ecapio capparms reg. */
Clegacy = 1, /* legacy support cap. id */
CLbiossem = 2, /* legacy cap. bios sem. */
CLossem = 3, /* legacy cap. os sem */
CLcontrol = 4, /* legacy support control & status */
/* typed links */
Lterm = 1,
Litd = 0<<1,
Lqh = 1<<1,
Lsitd = 2<<1,
Lfstn = 3<<1, /* we don't use these */
/* Cmd reg. */
Cstop = 0x00000, /* stop running */
Crun = 0x00001, /* start operation */
Chcreset = 0x00002, /* host controller reset */
Cflsmask = 0x0000C, /* frame list size bits */
Cfls1024 = 0x00000, /* frame list size 1024 */
Cfls512 = 0x00004, /* frame list size 512 frames */
Cfls256 = 0x00008, /* frame list size 256 frames */
Cpse = 0x00010, /* periodic sched. enable */
Case = 0x00020, /* async sched. enable */
Ciasync = 0x00040, /* interrupt on async advance doorbell */
Citc1 = 0x10000, /* interrupt threshold ctl. 1 µframe */
Citc4 = 0x40000, /* same. 2 µframes */
/* ... */
Citc8 = 0x80000, /* same. 8 µframes (can go up to 64) */
/* Sts reg. */
Sasyncss = 0x08000, /* aync schedule status */
Speriodss = 0x04000, /* periodic schedule status */
Srecl = 0x02000, /* reclamnation (empty async sched.) */
Shalted = 0x01000, /* h.c. is halted */
Sasync = 0x00020, /* interrupt on async advance */
Sherr = 0x00010, /* host system error */
Sfrroll = 0x00008, /* frame list roll over */
Sportchg = 0x00004, /* port change detect */
Serrintr = 0x00002, /* error interrupt */
Sintr = 0x00001, /* interrupt */
Sintrs = 0x0003F, /* interrupts status */
/* Intr reg. */
Iusb = 0x01, /* intr. on usb */
Ierr = 0x02, /* intr. on usb error */
Iportchg = 0x04, /* intr. on port change */
Ifrroll = 0x08, /* intr. on frlist roll over */
Ihcerr = 0x10, /* intr. on host error */
Iasync = 0x20, /* intr. on async advance enable */
Iall = 0x3F, /* all interrupts */
/* Config reg. */
Callmine = 1, /* route all ports to us */
/* Portsc reg. */
Pspresent = 0x00000001, /* device present */
Psstatuschg = 0x00000002, /* Pspresent changed */
Psenable = 0x00000004, /* device enabled */
Pschange = 0x00000008, /* Psenable changed */
Psresume = 0x00000040, /* resume detected */
Pssuspend = 0x00000080, /* port suspended */
Psreset = 0x00000100, /* port reset */
Pspower = 0x00001000, /* port power on */
Psowner = 0x00002000, /* port owned by companion */
Pslinemask = 0x00000C00, /* line status bits */
Pslow = 0x00000400, /* low speed device */
/* Debug port csw reg. */
Cowner = 0x40000000, /* port owned by ehci */
Cenable = 0x10000000, /* debug port enabled */
Cdone = 0x00010000, /* request is done */
Cbusy = 0x00000400, /* port in use by a driver */
Cerrmask= 0x00000380, /* error code bits */
Chwerr = 0x00000100, /* hardware error */
Cterr = 0x00000080, /* transaction error */
Cfailed = 0x00000040, /* transaction did fail */
Cgo = 0x00000020, /* execute the transaction */
Cwrite = 0x00000010, /* request is a write */
Clen = 0x0000000F, /* data len */
/* Debug port pid reg. */
Prpidshift = 16, /* received pid */
Prpidmask = 0xFF,
Pspidshift = 8, /* sent pid */
Pspidmask = 0xFF,
Ptokshift = 0, /* token pid */
Ptokmask = 0xFF,
Ptoggle = 0x00008800, /* to update toggles */
Ptogglemask = 0x0000FF00,
/* Debug port addr reg. */
Adevshift = 8, /* device address */
Adevmask = 0x7F,
Aepshift = 0, /* endpoint number */
Aepmask = 0xF,
};
/*
* Capability registers (hw)
*/
struct Ecapio
{
ulong cap; /* 00 controller capability register */
ulong parms; /* 04 structural parameters register */
ulong capparms; /* 08 capability parameters */
ulong portroute; /* 0c not on the CS5536 */
};
/*
* Debug port registers (hw)
*/
struct Edbgio
{
ulong csw; /* control and status */
ulong pid; /* USB pid */
uchar data[8]; /* data buffer */
ulong addr; /* device and endpoint addresses */
};
struct Poll
{
Lock;
@ -191,15 +56,6 @@ struct Ctlr
Poll poll;
};
/*
* OMAP3-specific stuff
*/
enum {
/* hostconfig bits */
P1ulpi_bypass = 1<<0, /* utmi if set; else ulpi */
};
/*
* Operational registers (hw)
*/
@ -233,6 +89,11 @@ struct Uhh {
ulong debug_csr;
};
enum {
/* hostconfig bits */
P1ulpi_bypass = 1<<0, /* utmi if set; else ulpi */
};
extern Ecapio *ehcidebugcapio;
extern int ehcidebugport;

144
sys/src/9/port/portusbehci.h Normal file
View file

@ -0,0 +1,144 @@
/*
* ECHI portable hardware definitions
*/
typedef struct Ecapio Ecapio;
typedef struct Edbgio Edbgio;
#pragma incomplete Ecapio;
#pragma incomplete Edbgio;
/*
* EHCI interface registers and bits
*/
enum
{
/* Ecapio->parms reg. */
Cnports = 0xF, /* nport bits */
Cdbgportshift = 20, /* debug port */
Cdbgportmask = 0xF,
/* Ecapio->capparms bits */
C64 = 1<<0, /* 64-bits */
Cpfl = 1<<1, /* program'ble frame list: can be <1024 */
Casp = 1<<2, /* asynch. sched. park */
Ceecpshift = 8, /* extended capabilities ptr. */
Ceecpmask = (1<<8) - 1,
Clegacy = 1, /* legacy support cap. id */
CLbiossem = 2, /* legacy cap. bios sem. */
CLossem = 3, /* legacy cap. os sem */
CLcontrol = 4, /* legacy support control & status */
/* typed links */
Lterm = 1,
Litd = 0<<1,
Lqh = 1<<1,
Lsitd = 2<<1,
Lfstn = 3<<1, /* we don't use these */
/* Cmd reg. */
Cstop = 0x00000, /* stop running */
Crun = 0x00001, /* start operation */
Chcreset = 0x00002, /* host controller reset */
Cflsmask = 0x0000C, /* frame list size bits */
Cfls1024 = 0x00000, /* frame list size 1024 */
Cfls512 = 0x00004, /* frame list size 512 frames */
Cfls256 = 0x00008, /* frame list size 256 frames */
Cpse = 0x00010, /* periodic sched. enable */
Case = 0x00020, /* async sched. enable */
Ciasync = 0x00040, /* interrupt on async advance doorbell */
/* interrupt threshold ctl. in µframes (1-32 in powers of 2) */
Citcshift = 16,
Citcmask = 0xff << Citcshift,
/* Sts reg. */
Sasyncss = 0x08000, /* aync schedule status */
Speriodss = 0x04000, /* periodic schedule status */
Srecl = 0x02000, /* reclamnation (empty async sched.) */
Shalted = 0x01000, /* h.c. is halted */
Sasync = 0x00020, /* interrupt on async advance */
Sherr = 0x00010, /* host system error */
Sfrroll = 0x00008, /* frame list roll over */
Sportchg = 0x00004, /* port change detect */
Serrintr = 0x00002, /* error interrupt */
Sintr = 0x00001, /* interrupt */
Sintrs = 0x0003F, /* interrupts status */
/* Intr reg. */
Iusb = 0x01, /* intr. on usb */
Ierr = 0x02, /* intr. on usb error */
Iportchg = 0x04, /* intr. on port change */
Ifrroll = 0x08, /* intr. on frlist roll over */
Ihcerr = 0x10, /* intr. on host error */
Iasync = 0x20, /* intr. on async advance enable */
Iall = 0x3F, /* all interrupts */
/* Config reg. */
Callmine = 1, /* route all ports to us */
/* Portsc reg. */
Pspresent = 0x00000001, /* device present */
Psstatuschg = 0x00000002, /* Pspresent changed */
Psenable = 0x00000004, /* device enabled */
Pschange = 0x00000008, /* Psenable changed */
Psresume = 0x00000040, /* resume detected */
Pssuspend = 0x00000080, /* port suspended */
Psreset = 0x00000100, /* port reset */
Pspower = 0x00001000, /* port power on */
Psowner = 0x00002000, /* port owned by companion */
Pslinemask = 0x00000C00, /* line status bits */
Pslow = 0x00000400, /* low speed device */
/* Debug port csw reg. */
Cowner = 0x40000000, /* port owned by ehci */
Cenable = 0x10000000, /* debug port enabled */
Cdone = 0x00010000, /* request is done */
Cbusy = 0x00000400, /* port in use by a driver */
Cerrmask= 0x00000380, /* error code bits */
Chwerr = 0x00000100, /* hardware error */
Cterr = 0x00000080, /* transaction error */
Cfailed = 0x00000040, /* transaction did fail */
Cgo = 0x00000020, /* execute the transaction */
Cwrite = 0x00000010, /* request is a write */
Clen = 0x0000000F, /* data len */
/* Debug port pid reg. */
Prpidshift = 16, /* received pid */
Prpidmask = 0xFF,
Pspidshift = 8, /* sent pid */
Pspidmask = 0xFF,
Ptokshift = 0, /* token pid */
Ptokmask = 0xFF,
Ptoggle = 0x00008800, /* to update toggles */
Ptogglemask = 0x0000FF00,
/* Debug port addr reg. */
Adevshift = 8, /* device address */
Adevmask = 0x7F,
Aepshift = 0, /* endpoint number */
Aepmask = 0xF,
};
/*
* Capability registers (hw)
*/
struct Ecapio
{
ulong cap; /* 00 controller capability register */
ulong parms; /* 04 structural parameters register */
ulong capparms; /* 08 capability parameters */
ulong portroute; /* 0c not on the CS5536 */
};
/*
* Debug port registers (hw)
*/
struct Edbgio
{
ulong csw; /* control and status */
ulong pid; /* USB pid */
uchar data[8]; /* data buffer */
ulong addr; /* device and endpoint addresses */
};