xfnw/plan9fox
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

imx8: fix fracpll code, enable 1.4Ghz turbo for arm

Browse source
This commit is contained in:
cinap_lenrek 2022-07-09 21:12:20 +00:00
parent 90f47fadf8
commit 414cefcb0b
2 changed files with 20 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
sys/src/9/imx8/ccm.c
View file

@ -146,7 +146,7 @@ enum {
}; };
static int input_clk_freq[] = { static int input_clk_freq[] = {
[ARM_PLL_CLK] 1600*Mhz, [ARM_PLL_CLK] 1400*Mhz,
[GPU_PLL_CLK] 1600*Mhz, [GPU_PLL_CLK] 1600*Mhz,
[VPU_PLL_CLK] 800*Mhz, [VPU_PLL_CLK] 800*Mhz,
[DRAM_PLL1_CLK] 800*Mhz, [DRAM_PLL1_CLK] 800*Mhz,
@ -977,25 +977,21 @@ enablefracpll(u32int *reg, int ref_sel, int ref_freq, int freq)
error = freq; error = freq;
for(divq = 2; divq <= 64; divq += 2){ for(divq = 2; divq <= 64; divq += 2){
for(divr = 1; divr <= 64; divr++){ for(divr = 2; divr <= 64; divr++){
ref = ref_freq/divr; ref = ref_freq/divr;
if(ref < 10*Mhz || ref > 300*Mhz)
v = (vlong)freq*divq;
v <<= 24;
v /= ref * 8;
divfi = v >> 24;
divff = v & 0xFFFFFF;
if(divfi < 1 || divfi > 128)
continue; continue;
ref *= 8; v *= (vlong)ref * 8;
divfi = ((vlong)freq*divq) / ref; v /= (vlong)divq << 24;
if(divfi < 1 || divfi > 32) pllout = v;
continue;
v = ((vlong)freq*divq) - (vlong)ref*divfi;
divff = (v<<24) / ref;
if(divff < 1 || divff > (1<<24))
continue;
v = (vlong)ref*(vlong)divff;
pllout = (ref*divfi + (v>>24))/divq;
if(pllout < 30*Mhz || pllout > 2000*Mhz)
continue;
if(pllout > freq) if(pllout > freq)
continue; continue;
@ -1003,16 +999,15 @@ enablefracpll(u32int *reg, int ref_sel, int ref_freq, int freq)
if(freq - pllout > error) if(freq - pllout > error)
continue; continue;
// iprint("%p enablefracpll: freq=%d (actual %d)\n", PADDR(reg), freq, pllout);
cfg0 = 1<<21 | ref_sel<<16 | 1<<15 | (divr-1)<<5 | (divq/2)-1; cfg0 = 1<<21 | ref_sel<<16 | 1<<15 | (divr-1)<<5 | (divq/2)-1;
cfg1 = divff<<7 | divfi-1; cfg1 = divff<<7 | (divfi-1);
error = freq - pllout; error = freq - pllout;
if(error == 0) if(error == 0)
goto Found; goto Found;
} }
} }
panic("enablefracpll: %#p freq %d: out of range", PADDR(reg), freq);
Found: Found:
/* skip if nothing has changed */ /* skip if nothing has changed */
@ -1022,19 +1017,16 @@ Found:
reg[0] |= 1<<14; /* bypass */ reg[0] |= 1<<14; /* bypass */
// iprint("%p cfg1=%.8ux\n", PADDR(reg), cfg1);
reg[1] = cfg1; reg[1] = cfg1;
// iprint("%p cfg0=%.8ux\n", PADDR(reg), cfg0);
reg[0] = cfg0 | (1<<14) | (1<<12); reg[0] = cfg0 | (1<<14) | (1<<12);
/* unbypass */ /* unbypass */
reg[0] &= ~(1<<14); reg[0] &= ~(1<<14);
// iprint("%p wait for lock...", PADDR(reg));
while((reg[0] & (1<<31)) == 0) while((reg[0] & (1<<31)) == 0)
; ;
// iprint("locked!\n");
reg[0] &= ~(1<<12); reg[0] &= ~(1<<12);
} }

4
sys/src/9/imx8/clock.c
View file

@ -43,6 +43,10 @@ clockinit(void)
if(m->machno == 0){ if(m->machno == 0){
freq = sysrd(CNTFRQ_EL0); freq = sysrd(CNTFRQ_EL0);
print("timer frequency %lld Hz\n", freq); print("timer frequency %lld Hz\n", freq);
/* TURBO! */
setclkrate("ccm_arm_a53_clk_root", "osc_25m_ref_clk", 25*Mhz);
setclkrate("ccm_arm_a53_clk_root", "arm_pll_clk", 1400*Mhz);
} }
tstart = sysrd(CNTPCT_EL0); tstart = sysrd(CNTPCT_EL0);
do{ do{