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pc/vga*: use 64-bit physical addresses and check pci membar types and sizes

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This commit is contained in:
cinap_lenrek 2020-06-06 15:58:18 +02:00
parent a8f64e53fe
commit 3bebd3f5e2
16 changed files with 70 additions and 40 deletions
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3
sys/src/9/pc/vga3dfx.c
View file

@ -37,8 +37,9 @@ tdfxenable(VGAscr* scr)
if(scr->mmio) if(scr->mmio)
return; return;
p = scr->pci; p = scr->pci;
if(p == nil || p->vid != 0x121A) if(p == nil || p->vid != 0x121A || (p->mem[0].bar & 1) != 0)
return; return;
scr->mmio = vmap(p->mem[0].bar&~0x0F, p->mem[0].size); scr->mmio = vmap(p->mem[0].bar&~0x0F, p->mem[0].size);
if(scr->mmio == nil) if(scr->mmio == nil)
return; return;

6
sys/src/9/pc/vgaclgd546x.c
View file

@ -42,8 +42,10 @@ clgd546xenable(VGAscr* scr)
p = scr->pci; p = scr->pci;
if(p == nil) if(p == nil)
return; return;
if(p->mem[1].bar & 1)
return;
scr->mmio = vmap(p->mem[1].bar&~0x0F, p->mem[1].size); scr->mmio = vmap(p->mem[1].bar&~0x0F, p->mem[1].size);
if(scr->mmio == 0) if(scr->mmio == nil)
return; return;
addvgaseg("clgd546xmmio", p->mem[1].bar&~0x0F, p->mem[1].size); addvgaseg("clgd546xmmio", p->mem[1].bar&~0x0F, p->mem[1].size);
} }
@ -53,7 +55,7 @@ clgd546xcurdisable(VGAscr* scr)
{ {
Cursor546x *cursor546x; Cursor546x *cursor546x;
if(scr->mmio == 0) if(scr->mmio == nil)
return; return;
cursor546x = (Cursor546x*)((uchar*)scr->mmio+CursorMMIO); cursor546x = (Cursor546x*)((uchar*)scr->mmio+CursorMMIO);
cursor546x->enable = 0; cursor546x->enable = 0;

2
sys/src/9/pc/vgacyber938x.c
View file

@ -56,7 +56,7 @@ cyber938xlinear(VGAscr* scr, int, int)
* Heuristic to detect the MMIO space. We're flying blind * Heuristic to detect the MMIO space. We're flying blind
* here, with only the XFree86 source to guide us. * here, with only the XFree86 source to guide us.
*/ */
if(p->mem[1].size == 0x20000) if(p->mem[1].size == 0x20000 && (p->mem[1].bar & 1) == 0)
scr->mmio = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size); scr->mmio = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size);
if(scr->apsize) if(scr->apsize)

8
sys/src/9/pc/vgageode.c
View file

@ -32,9 +32,13 @@ geodeenable(VGAscr* scr)
if(scr->mmio) if(scr->mmio)
return; return;
p = scr->pci; p = scr->pci;
if(!p) return; if(p == nil)
return;
if((p->mem[1].bar | p->mem[2].bar | p->mem[3].bar) & 1)
return;
scr->mmio = vmap(p->mem[2].bar&~0x0F, p->mem[2].size); scr->mmio = vmap(p->mem[2].bar&~0x0F, p->mem[2].size);
if(!scr->mmio) return; if(scr->mmio == nil)
return;
addvgaseg("geodegp", p->mem[1].bar&~0x0F, p->mem[1].size); addvgaseg("geodegp", p->mem[1].bar&~0x0F, p->mem[1].size);
addvgaseg("geodemmio", p->mem[2].bar&~0x0F, p->mem[2].size); addvgaseg("geodemmio", p->mem[2].bar&~0x0F, p->mem[2].size);
addvgaseg("geodevid", p->mem[3].bar&~0x0F, p->mem[3].size); addvgaseg("geodevid", p->mem[3].bar&~0x0F, p->mem[3].size);

8
sys/src/9/pc/vgai81x.c
View file

@ -55,15 +55,19 @@ i81xenable(VGAscr* scr)
{ {
Pcidev *p; Pcidev *p;
int size; int size;
ulong *pgtbl, *rp, fbuf, fbend; ulong *pgtbl, *rp;
uintptr fbuf, fbend;
if(scr->mmio) if(scr->mmio)
return; return;
p = scr->pci; p = scr->pci;
if(p == nil) if(p == nil)
return; return;
if((p->mem[0].bar & 1) != 0
|| (p->mem[1].bar & 1) != 0)
return;
scr->mmio = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size); scr->mmio = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size);
if(scr->mmio == 0) if(scr->mmio == nil)
return; return;
addvgaseg("i81xmmio", p->mem[1].bar&~0x0F, p->mem[1].size); addvgaseg("i81xmmio", p->mem[1].bar&~0x0F, p->mem[1].size);

2
sys/src/9/pc/vgaigfx.c
View file

@ -42,6 +42,8 @@ igfxenable(VGAscr* scr)
p = scr->pci; p = scr->pci;
if(p == nil) if(p == nil)
return; return;
if(p->mem[0].bar & 1)
return;
scr->mmio = vmap(p->mem[0].bar&~0x0F, p->mem[0].size); scr->mmio = vmap(p->mem[0].bar&~0x0F, p->mem[0].size);
if(scr->mmio == nil) if(scr->mmio == nil)
return; return;

3
sys/src/9/pc/vgamach64xx.c
View file

@ -174,7 +174,6 @@ mach64xxenable(VGAscr* scr)
* this will do for now. * this will do for now.
*/ */
scr->io = p->mem[1].bar & ~0x03; scr->io = p->mem[1].bar & ~0x03;
if(scr->io == 0) if(scr->io == 0)
scr->io = 0x2EC; scr->io = 0x2EC;
} }
@ -1068,7 +1067,7 @@ ovl_status(VGAscr *scr, Chan *, char **field)
mach64type->m64_ovlclock, mach64type->m64_ovlclock,
mach64revb? "yes": "no", mach64revb? "yes": "no",
mach64refclock); mach64refclock);
pprint("%s: storage @%.8luX, aperture @%8.ulX, ovl buf @%.8ulX\n", pprint("%s: storage @%.8luX, aperture @%8.ullX, ovl buf @%.8ulX\n",
scr->dev->name, scr->storage, scr->paddr, scr->dev->name, scr->storage, scr->paddr,
mach64overlay); mach64overlay);
} }

4
sys/src/9/pc/vgamga2164w.c
View file

@ -40,6 +40,10 @@ mga2164wenable(VGAscr* scr)
if(p == nil || p->vid != MATROX) if(p == nil || p->vid != MATROX)
return; return;
if((p->mem[0].bar & 1) != 0
|| (p->mem[1].bar & 1) != 0)
return;
if(p->did == MGA2064){ if(p->did == MGA2064){
scr->mmio = vmap(p->mem[0].bar&~0x0F, p->mem[0].size); scr->mmio = vmap(p->mem[0].bar&~0x0F, p->mem[0].size);
if(scr->mmio == nil) if(scr->mmio == nil)

15
sys/src/9/pc/vgamga4xx.c
View file

@ -119,17 +119,22 @@ mga4xxenable(VGAscr* scr)
if(pci == nil) if(pci == nil)
return; return;
/* need to map frame buffer here too, so vga can find memory size */
if(pci->did == MGA4xx || pci->did == MGA550)
size = 32*MB;
else
size = 8*MB;
if((pci->mem[0].bar & 1) != 0 || pci->mem[0].size < size
|| (pci->mem[1].bar & 1) != 0 || pci->mem[1].size < 16*1024)
return;
scr->mmio = vmap(pci->mem[1].bar&~0x0F, 16*1024); scr->mmio = vmap(pci->mem[1].bar&~0x0F, 16*1024);
if(scr->mmio == nil) if(scr->mmio == nil)
return; return;
addvgaseg("mga4xxmmio", pci->mem[1].bar&~0x0F, pci->mem[1].size); addvgaseg("mga4xxmmio", pci->mem[1].bar&~0x0F, pci->mem[1].size);
/* need to map frame buffer here too, so vga can find memory size */
if(pci->did == MGA4xx || pci->did == MGA550)
size = 32*MB;
else
size = 8*MB;
vgalinearaddr(scr, pci->mem[0].bar&~0x0F, size); vgalinearaddr(scr, pci->mem[0].bar&~0x0F, size);
if(scr->paddr){ if(scr->paddr){

30
sys/src/9/pc/vganeomagic.c
View file

@ -26,8 +26,8 @@ static void
neomagicenable(VGAscr* scr) neomagicenable(VGAscr* scr)
{ {
Pcidev *p; Pcidev *p;
int curoff, vmsize; int bar, curoff, vmsize;
ulong ioaddr; uvlong ioaddr;
ulong iosize; ulong iosize;
/* /*
@ -42,48 +42,46 @@ neomagicenable(VGAscr* scr)
p = scr->pci; p = scr->pci;
if(p == nil || p->vid != 0x10C8) if(p == nil || p->vid != 0x10C8)
return; return;
bar = 1;
switch(p->did){ switch(p->did){
case 0x0003: /* MagicGraph 128ZV */ case 0x0003: /* MagicGraph 128ZV */
bar = 0;
if(p->mem[bar].bar & 1)
return;
ioaddr = (p->mem[bar].bar & ~0x0F) + 0x200000;
iosize = 0x200000;
curoff = 0x100; curoff = 0x100;
vmsize = 1152*1024; vmsize = 1152*1024;
ioaddr = (p->mem[0].bar & ~0x0F) + 0x200000; goto Map;
iosize = 0x200000;
break;
case 0x0083: /* MagicGraph 128ZV+ */ case 0x0083: /* MagicGraph 128ZV+ */
curoff = 0x100; curoff = 0x100;
vmsize = 1152*1024; vmsize = 1152*1024;
ioaddr = p->mem[1].bar & ~0x0F;
iosize = p->mem[1].size;
break; break;
case 0x0004: /* MagicGraph 128XD */ case 0x0004: /* MagicGraph 128XD */
curoff = 0x100; curoff = 0x100;
vmsize = 2048*1024; vmsize = 2048*1024;
ioaddr = p->mem[1].bar & ~0x0F;
iosize = p->mem[1].size;
break; break;
case 0x0005: /* MagicMedia 256AV */ case 0x0005: /* MagicMedia 256AV */
curoff = 0x1000; curoff = 0x1000;
vmsize = 2560*1024; vmsize = 2560*1024;
ioaddr = p->mem[1].bar & ~0x0F;
iosize = p->mem[1].size;
break; break;
case 0x0006: /* MagicMedia 256ZX */ case 0x0006: /* MagicMedia 256ZX */
curoff = 0x1000; curoff = 0x1000;
vmsize = 4096*1024; vmsize = 4096*1024;
ioaddr = p->mem[1].bar & ~0x0F;
iosize = p->mem[1].size;
break; break;
case 0x0016: /* MagicMedia 256XL+ */ case 0x0016: /* MagicMedia 256XL+ */
curoff = 0x1000; curoff = 0x1000;
/* Vaio VESA BIOS says 6080, but then hwgc doesn't work */ /* Vaio VESA BIOS says 6080, but then hwgc doesn't work */
vmsize = 4096*1024; vmsize = 4096*1024;
ioaddr = p->mem[1].bar & ~0x0F;
iosize = p->mem[1].size;
break; break;
default: default:
return; return;
} }
if(p->mem[bar].bar & 1)
return;
ioaddr = p->mem[bar].bar & ~0x0F;
iosize = p->mem[bar].size;
Map:
scr->mmio = vmap(ioaddr, iosize); scr->mmio = vmap(ioaddr, iosize);
if(scr->mmio == nil) if(scr->mmio == nil)
return; return;

3
sys/src/9/pc/vganvidia.c
View file

@ -90,7 +90,8 @@ nvidiaenable(VGAscr* scr)
if(p == nil) if(p == nil)
return; return;
scr->id = p->did; scr->id = p->did;
if(p->mem[0].bar & 1)
return;
scr->mmio = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size); scr->mmio = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
if(scr->mmio == nil) if(scr->mmio == nil)
return; return;

5
sys/src/9/pc/vgaradeon.c
View file

@ -87,9 +87,10 @@ radeonenable(VGAscr *scr)
if (p == nil) if (p == nil)
return; return;
scr->id = p->did; scr->id = p->did;
if(p->mem[2].bar & 1)
return;
scr->mmio = vmap(p->mem[2].bar & ~0x0f, p->mem[2].size); scr->mmio = vmap(p->mem[2].bar & ~0x0f, p->mem[2].size);
if(scr->mmio == 0) if(scr->mmio == nil)
return; return;
addvgaseg("radeonmmio", p->mem[2].bar & ~0x0f, p->mem[2].size); addvgaseg("radeonmmio", p->mem[2].bar & ~0x0f, p->mem[2].size);

3
sys/src/9/pc/vgas3.c
View file

@ -91,8 +91,9 @@ s3page(VGAscr* scr, int page)
static void static void
s3linear(VGAscr* scr, int, int) s3linear(VGAscr* scr, int, int)
{ {
uvlong mmiobase;
ulong mmiosize;
int id, j; int id, j;
ulong mmiobase, mmiosize;
Pcidev *p; Pcidev *p;
p = scr->pci; p = scr->pci;

3
sys/src/9/pc/vgat2r4.c
View file

@ -67,7 +67,8 @@ t2r4enable(VGAscr* scr)
p = scr->pci; p = scr->pci;
if(p == nil) if(p == nil)
return; return;
if(p->mem[4].bar & 1)
return;
mmio = vmap(p->mem[4].bar & ~0x0F, p->mem[4].size); mmio = vmap(p->mem[4].bar & ~0x0F, p->mem[4].size);
if(mmio == nil) if(mmio == nil)
return; return;

4
sys/src/9/pc/vgavesa.c
View file

@ -161,9 +161,9 @@ vesalinear(VGAscr *scr, int, int)
if(pci->ccrb != Pcibcdisp) if(pci->ccrb != Pcibcdisp)
continue; continue;
for(i=0; i<nelem(pci->mem); i++){ for(i=0; i<nelem(pci->mem); i++){
ulong a, e; uvlong a, e;
if(pci->mem[i].bar&1) /* not memory */ if(pci->mem[i].size == 0 || (pci->mem[i].bar & 1) != 0)
continue; continue;
a = pci->mem[i].bar & ~0xF; a = pci->mem[i].bar & ~0xF;
e = a + pci->mem[i].size; e = a + pci->mem[i].size;

11
sys/src/9/pc/vgavmware.c
View file

@ -95,7 +95,7 @@ enum {
typedef struct Vmware Vmware; typedef struct Vmware Vmware;
struct Vmware { struct Vmware {
ulong fb; uvlong fb;
ulong ra; ulong ra;
ulong rd; ulong rd;
@ -142,6 +142,8 @@ vmwarelinear(VGAscr* scr, int, int)
p = scr->pci; p = scr->pci;
if(p == nil || p->vid != PCIVMWARE) if(p == nil || p->vid != PCIVMWARE)
return; return;
if(p->mem[1].bar & 1)
return;
switch(p->did){ switch(p->did){
default: default:
return; return;
@ -151,6 +153,8 @@ vmwarelinear(VGAscr* scr, int, int)
vm->rd = 0x4560 + 4; vm->rd = 0x4560 + 4;
break; break;
case VMWARE2: case VMWARE2:
if((p->mem[0].bar & 1) == 0)
return;
vm->ver = 2; vm->ver = 2;
vm->ra = p->mem[0].bar & ~3; vm->ra = p->mem[0].bar & ~3;
vm->rd = vm->ra + 1; vm->rd = vm->ra + 1;
@ -164,8 +168,11 @@ vmwarelinear(VGAscr* scr, int, int)
addvgaseg("vmwarescreen", scr->paddr, scr->apsize); addvgaseg("vmwarescreen", scr->paddr, scr->apsize);
if(scr->mmio==nil){ if(scr->mmio==nil){
ulong mmiobase, mmiosize; uvlong mmiobase;
ulong mmiosize;
if(p->mem[2].bar & 1)
return;
// mmiobase = vmrd(vm, Rmemstart); // mmiobase = vmrd(vm, Rmemstart);
mmiobase = p->mem[2].bar & ~0xF; mmiobase = p->mem[2].bar & ~0xF;
if(mmiobase == 0) if(mmiobase == 0)