diff --git a/sys/src/9/imx8/lcd.c b/sys/src/9/imx8/lcd.c
index 3b39a6c74..e69f6ff96 100644
--- a/sys/src/9/imx8/lcd.c
+++ b/sys/src/9/imx8/lcd.c
@@ -440,6 +440,14 @@ dsiparams(struct dsi_cfg *cfg, int lanes, int hs_clk, int ref_clk, int tx_esc_cl
 	cfg->wakeup_ps = 1000000000000LL;
 }
 
+static void
+lcdifreset(void)
+{
+	wr(lcdif, LCDIF_CTRL_SET, CTRL_SFTRST);
+	delay(1);
+	wr(lcdif, LCDIF_CTRL_SET, CTRL_CLKGATE);
+}
+
 static void
 lcdifinit(struct video_mode *mode)
 {
@@ -501,6 +509,11 @@ bridgeinit(I2Cdev *dev, struct video_mode *mode, struct dsi_cfg *cfg)
 {
 	int n;
 
+	// soft reset
+	i2cwritebyte(dev, 0x09, 1);
+	while(i2creadbyte(dev, 0x09) & 1)
+		;
+
 	// clock derived from dsi clock
 	switch(cfg->hs_clk/2000000){
 	case 384:
@@ -838,8 +851,10 @@ lcdinit(void)
 	gpioout(GPIO_PIN(3, 20), 1);
 
 	bridge = i2cdev(i2cbus("i2c4"), 0x2C);
-	if(bridge == nil)
-		return;
+	if(bridge == nil){
+		err = "could not find bridge";
+		goto out;
+	}
 	bridge->subaddr = 1;
 
 	/* power on mipi dsi */
@@ -858,6 +873,8 @@ lcdinit(void)
 	setclkgate("disp.axi_clk", 1);
 	setclkgate("sim_display.mainclk", 1);
 
+	lcdifreset();
+
 	setclkrate("mipi.core", "system_pll1_div3", 266*Mhz);
 	setclkrate("mipi.CLKREF", "system_pll2_clk", 25*Mhz);
 	setclkrate("mipi.RxClkEsc", "system_pll1_clk", 80*Mhz);