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usbxhci: delay after reset, preserve reserved bits in legacy status control register in handoff()

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when clering smi enable bits in the legacy control/status register,
preserve the reserved bits. clear the RW1C bits.

linux code claims intel xhci controller needs a 1ms delay before
accessing any register after reset.
This commit is contained in:
cinap_lenrek 2018-10-08 07:05:28 +02:00
parent a71a57f8f2
commit 2fecc5789e
1 changed files with 6 additions and 2 deletions
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8
sys/src/9/pc/usbxhci.c
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@ -397,9 +397,12 @@ handoff(Ctlr *ctlr)
r[0] |= 1<<24; /* request ownership */ r[0] |= 1<<24; /* request ownership */
for(i = 0; (r[0] & (1<<16)) != 0 && i<100; i++) for(i = 0; (r[0] & (1<<16)) != 0 && i<100; i++)
tsleep(&up->sleep, return0, nil, 10); tsleep(&up->sleep, return0, nil, 10);
r[0] &= ~(1<<16); /* in case of timeout */
} }
r[1] = 0; /* disable SMI interrupts */ /* disable SMI interrupts */
r[1] = (r[1] & (7<<1 | 255<<5 | 7<<17)) | 7<<29;
/* clear BIOS ownership in case of timeout */
r[0] &= ~(1<<16);
} }
static void static void
@ -462,6 +465,7 @@ init(Hci *hp)
tsleep(&up->sleep, return0, nil, 10); tsleep(&up->sleep, return0, nil, 10);
ctlr->opr[USBCMD] = HCRST; ctlr->opr[USBCMD] = HCRST;
delay(1);
for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != HCH && i<100; i++) for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != HCH && i<100; i++)
tsleep(&up->sleep, return0, nil, 10); tsleep(&up->sleep, return0, nil, 10);