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ether8169: and phy wakeup and reset phy before enabling auto negotiation

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this brings up the 8198B on BurnZeZ's ASRock Z68 Professional Gen3 board.
This commit is contained in:
cinap_lenrek 2013-05-12 02:58:02 +02:00
parent 25bc4e84e9
commit 29ece7fda4
1 changed files with 14 additions and 1 deletions
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15
sys/src/9/pc/ether8169.c
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@ -50,6 +50,8 @@ enum { /* registers */
Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */ Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */ Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
Phystatus = 0x6C, /* PHY Status */ Phystatus = 0x6C, /* PHY Status */
Pmch = 0x6F, /* power management */
Ldps = 0x82, /* link down power saving */
Rms = 0xDA, /* Receive Packet Maximum Size */ Rms = 0xDA, /* Receive Packet Maximum Size */
Cplusc = 0xE0, /* C+ Command */ Cplusc = 0xE0, /* C+ Command */
@ -387,13 +389,20 @@ rtl8169mii(Ctlr* ctlr)
ctlr->mii->miw = rtl8169miimiw; ctlr->mii->miw = rtl8169miimiw;
ctlr->mii->ctlr = ctlr; ctlr->mii->ctlr = ctlr;
/*
* PHY wakeup
*/
csr8w(ctlr, Pmch, csr8r(ctlr, Pmch) | 0x80);
rtl8169miimiw(ctlr->mii, 1, 0x1f, 0);
rtl8169miimiw(ctlr->mii, 1, 0x0e, 0);
/* /*
* Get rev number out of Phyidr2 so can config properly. * Get rev number out of Phyidr2 so can config properly.
* There's probably more special stuff for Macv0[234] needed here. * There's probably more special stuff for Macv0[234] needed here.
*/ */
ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F; ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
if(ctlr->macv == Macv02){ if(ctlr->macv == Macv02){
csr8w(ctlr, 0x82, 1); /* magic */ csr8w(ctlr, Ldps, 1); /* magic */
rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */ rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
} }
@ -405,6 +414,10 @@ rtl8169mii(Ctlr* ctlr)
print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n", print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
phy->oui, phy->phyno, ctlr->macv, ctlr->phyv); phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
miireset(ctlr->mii);
microdelay(100);
miiane(ctlr->mii, ~0, ~0, ~0); miiane(ctlr->mii, ~0, ~0, ~0);
return 0; return 0;