pc, pc64: new MTRR code supporting AMD TOM2 MSR and fixed mtrr ranges
The new MTRR code handles overlapping ranges and supports AMD specific TOM2 MSR. The format in /dev/archctl now only shows the effective cache ranges only, without exposing the low level registers.
This commit is contained in:
cinap_lenrek
parent
e6684dbfda
commit
2594b99629
1 changed files with 651 additions and 255 deletions
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@ -1,11 +1,3 @@
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/*
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* memory-type region registers.
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*
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* due to the possibility of extended addresses (for PAE)
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* as large as 36 bits coming from the e820 memory map and the like,
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* we'll use vlongs to hold addresses and lengths, even though we don't
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* implement PAE in Plan 9.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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@ -20,25 +12,59 @@ enum {
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*/
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MTRRPhysBase0 = 0x200,
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MTRRPhysMask0 = 0x201,
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MTRRDefaultType = 0x2FF,
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MTRRCap = 0xFE,
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Nmtrr = 8,
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/* cpuid extended function codes */
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Exthighfunc = 1ul << 31,
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Extprocsigamd,
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Extprocname0,
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Extprocname1,
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Extprocname2,
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Exttlbl1,
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Extl2,
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Extapm,
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Extaddrsz,
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MTRRDefaultType = 0x2FF,
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Deftype = 0xFF, /* default MTRR type */
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Deffixena = 1<<10, /* fixed-range MTRR enable */
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Defena = 1<<11, /* MTRR enable */
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MTRRCap = 0xFE,
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Capvcnt = 0xFF, /* mask: # of variable-range MTRRs we have */
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Capwc = 1<<8, /* flag: have write combining? */
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Capfix = 1<<10, /* flag: have fixed MTRRs? */
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AMDK8SysCfg = 0xC0010010,
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Tom2Enabled = 1<<21,
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Tom2ForceMemTypeWB = 1<<22,
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AMDK8TopMem2 = 0xC001001D,
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};
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enum {
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CR4PageGlobalEnable = 1 << 7,
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CR0CacheDisable = 1 << 30,
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Nvarreg = 8,
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Nfixreg = 11*8,
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Nranges = Nfixreg+Nvarreg*2+1,
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};
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typedef struct Varreg Varreg;
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struct Varreg {
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vlong base;
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vlong mask;
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};
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typedef struct Fixreg Fixreg;
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struct Fixreg {
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int msr;
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ulong base;
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ulong size;
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};
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typedef struct State State;
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struct State {
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uvlong mask;
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vlong cap;
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vlong def;
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vlong tom2;
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int nvarreg;
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Varreg varreg[Nvarreg];
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vlong fixreg[Nfixreg/8];
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};
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typedef struct Range Range;
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struct Range {
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uvlong base;
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uvlong size;
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int type;
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};
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enum {
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@ -51,37 +77,16 @@ enum {
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Writeback = 6,
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};
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enum {
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Capvcnt = 0xff, /* mask: # of variable-range MTRRs we have */
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Capwc = 1<<8, /* flag: have write combining? */
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Capfix = 1<<10, /* flag: have fixed MTRRs? */
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Deftype = 0xff, /* default MTRR type */
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Deffixena = 1<<10, /* fixed-range MTRR enable */
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Defena = 1<<11, /* MTRR enable */
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};
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typedef struct Mtrreg Mtrreg;
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typedef struct Mtrrop Mtrrop;
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struct Mtrreg {
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vlong base;
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vlong mask;
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};
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static char *types[] = {
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[Uncacheable] "uc",
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[Writecomb] "wc",
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[Unknown1] "uk1",
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[Unknown2] "uk2",
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[Writethru] "wt",
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[Writeprot] "wp",
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[Writeback] "wb",
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nil
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[Uncacheable] "uc",
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[Writecomb] "wc",
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[Unknown1] "uk1",
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[Unknown2] "uk2",
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[Writethru] "wt",
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[Writeprot] "wp",
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[Writeback] "wb",
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};
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static int dosync;
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static Mtrreg mtrreg[Nmtrr];
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static char *
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type2str(int type)
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{
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@ -93,137 +98,635 @@ type2str(int type)
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static int
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str2type(char *str)
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{
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char **p;
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int type;
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for(p = types; *p != nil; p++)
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if (strcmp(str, *p) == 0)
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return p - types;
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for(type = 0; type < nelem(types); type++){
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if(strcmp(str, types[type]) == 0)
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return type;
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}
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return -1;
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}
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static int
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getvarreg(State *s, Range *rp, int index)
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{
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Varreg *reg = &s->varreg[index];
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if((reg->mask & (1<<11)) == 0)
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return 0;
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rp->base = reg->base & ~0xFFFULL;
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rp->type = reg->base & 0xFF;
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rp->size = (s->mask ^ (reg->mask & ~0xFFFULL)) + 1;
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return 1;
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}
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static void
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setvarreg(State *s, Range *rp, int index)
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{
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Varreg *reg = &s->varreg[index];
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if(rp == nil || rp->size == 0){
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reg->base = 0;
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reg->mask = 0;
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return;
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}
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reg->base = rp->base | (rp->type & 0xFF);
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reg->mask = (s->mask & ~(rp->size-1)) | 1<<11;
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}
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static Fixreg fixreg[Nfixreg/8] = {
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0x250, 0x00000, 0x10000,
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0x258, 0x80000, 0x04000,
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0x259, 0xA0000, 0x04000,
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0x268, 0xC0000, 0x01000,
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0x269, 0xC8000, 0x01000,
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0x26A, 0xD0000, 0x01000,
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0x26B, 0xD8000, 0x01000,
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0x26C, 0xE0000, 0x01000,
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0x26D, 0xE8000, 0x01000,
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0x26E, 0xF0000, 0x01000,
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0x26F, 0xF8000, 0x01000,
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};
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static int
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getfixreg(State *s, Range *rp, int index)
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{
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Fixreg *reg = &fixreg[index >> 3];
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index &= 7;
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rp->base = reg->base + reg->size * index;
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rp->size = reg->size;
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rp->type = ((uvlong)s->fixreg[reg - fixreg] >> 8*index) & 0xFF;
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return 1;
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}
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static void
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setfixreg(State *s, Range *rp, int index)
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{
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Fixreg *reg = &fixreg[index >> 3];
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int type;
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index &= 7;
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if(rp == nil || rp->size == 0)
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type = Uncacheable;
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else
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type = rp->type & 0xFF;
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s->fixreg[reg - fixreg] &= ~(0xFFULL << 8*index);
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s->fixreg[reg - fixreg] |= (uvlong)type << 8*index;
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}
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static int
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preftype(int a, int b)
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{
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if(a == b)
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return a;
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if(a == Uncacheable || b == Uncacheable)
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return Uncacheable;
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if(a == Writethru && b == Writeback
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|| a == Writeback && b == Writethru)
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return Writethru;
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return -1;
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}
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static int
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gettype(State *s, uvlong pa, Range *new)
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{
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int i, type;
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Range r;
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if(new != nil && pa >= new->base && pa < new->base + new->size)
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return new->type;
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if((s->def & Defena) == 0)
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return Uncacheable;
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if(pa < 0x100000 && (s->def & Deffixena) != 0){
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for(i = 0; i < Nfixreg; i++){
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if(getfixreg(s, &r, i) && pa < r.base + r.size && pa >= r.base)
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return r.type;
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}
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}
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if(pa >= 0x100000000ULL && pa < s->tom2)
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return Writeback;
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type = -1;
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for(i = 0; i < s->nvarreg; i++){
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if(!getvarreg(s, &r, i))
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continue;
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if((pa & -r.size) == r.base)
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type = (type == -1) ? r.type : preftype(r.type, type);
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}
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if(type == -1)
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type = s->def & Deftype;
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return type;
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}
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static uvlong
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getnext(State *s, uvlong pa, Range *new)
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{
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uvlong end;
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Range r;
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int i;
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if(new != nil){
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end = getnext(s, pa, nil);
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if(pa < new->base && end > new->base)
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return new->base;
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if(pa < new->base + new->size && end > new->base + new->size)
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return new->base + new->size;
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return end;
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}
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end = s->mask+1;
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if((s->def & Defena) == 0)
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return end;
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if(pa < 0x100000 && (s->def & Deffixena) != 0){
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for(i = 0; i < Nfixreg; i++){
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if(getfixreg(s, &r, i) && pa < r.base + r.size && pa >= r.base)
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return r.base + r.size;
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}
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}
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if(pa >= 0x100000000ULL && pa < s->tom2)
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return s->tom2;
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for(i = 0; i < s->nvarreg; i++){
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if(!getvarreg(s, &r, i))
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continue;
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if((pa & -r.size) == r.base)
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r.base += r.size;
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else if(r.base <= pa)
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continue;
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if(r.base < end)
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end = r.base;
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}
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if(pa < 0x100000000ULL && end > 0x100000000ULL)
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end = 0x100000000ULL;
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return end;
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}
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enum {
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Exthighfunc = 1ul << 31,
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Extprocsigamd,
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Extprocname0,
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Extprocname1,
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Extprocname2,
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Exttlbl1,
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Extl2,
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Extapm,
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Extaddrsz,
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};
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static uvlong
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physmask(void)
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{
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ulong regs[4];
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static vlong mask = -1;
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uvlong mask;
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if (mask != -1)
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return mask;
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cpuid(Exthighfunc, regs);
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if(regs[0] >= Extaddrsz) { /* ax */
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cpuid(Extaddrsz, regs);
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mask = (1LL << (regs[0] & 0xFF)) - 1; /* ax */
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mask = (1ULL << (regs[0] & 0xFF)) - 1; /* ax */
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} else {
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mask &= (1LL << 36) - 1;
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mask = (1ULL << 36) - 1;
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}
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return mask;
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}
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static int
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ispow2(uvlong ul)
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getstate(State *s)
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{
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return (ul & (ul - 1)) == 0;
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vlong v;
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int i;
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s->mask = physmask();
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if(rdmsr(MTRRDefaultType, &s->def) < 0)
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return -1;
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if(rdmsr(MTRRCap, &s->cap) < 0)
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return -1;
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if(s->cap & Capfix){
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for(i = 0; i < nelem(fixreg); i++){
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if(rdmsr(fixreg[i].msr, &s->fixreg[i]) < 0)
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return -1;
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}
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} else {
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s->def &= ~(vlong)Deffixena;
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}
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s->nvarreg = s->cap & Capvcnt;
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if(s->nvarreg > Nvarreg)
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s->nvarreg = Nvarreg;
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for(i = 0; i < s->nvarreg; i++){
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if(rdmsr(MTRRPhysBase0 + 2*i, &s->varreg[i].base) < 0)
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return -1;
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if(rdmsr(MTRRPhysMask0 + 2*i, &s->varreg[i].mask) < 0)
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return -1;
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}
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if(strcmp(m->cpuidid, "AuthenticAMD") != 0
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|| m->cpuidfamily < 15
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|| rdmsr(AMDK8SysCfg, &v) < 0
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|| (v & (Tom2Enabled|Tom2ForceMemTypeWB)) != (Tom2Enabled|Tom2ForceMemTypeWB)
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|| rdmsr(AMDK8TopMem2, &s->tom2) < 0)
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s->tom2 = 0;
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else {
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s->tom2 &= s->mask;
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s->tom2 &= -0x800000LL;
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}
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return 0;
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}
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/* true if mtrr is valid */
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static int
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mtrrdec(Mtrreg *mtrr, uvlong *ptr, uvlong *size, int *type)
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{
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*ptr = mtrr->base & ~(BY2PG-1);
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*type = mtrr->base & 0xff;
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*size = (physmask() ^ (mtrr->mask & ~(BY2PG-1))) + 1;
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return (mtrr->mask >> 11) & 1;
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}
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enum {
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CR4PageGlobalEnable = 1 << 7,
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CR0CacheDisable = 1 << 30,
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};
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static void
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mtrrenc(Mtrreg *mtrr, uvlong ptr, uvlong size, int type, int ok)
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putstate(State *s)
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{
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mtrr->base = ptr | (type & 0xff);
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mtrr->mask = (physmask() & ~(size - 1)) | (ok? 1<<11: 0);
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}
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/*
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* i is the index of the MTRR, and is multiplied by 2 because
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* mask and base offsets are interleaved.
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*/
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static void
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mtrrget(Mtrreg *mtrr, uint i)
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{
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rdmsr(MTRRPhysBase0 + 2*i, &mtrr->base);
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rdmsr(MTRRPhysMask0 + 2*i, &mtrr->mask);
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}
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static void
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mtrrput(Mtrreg *mtrr, uint i)
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{
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wrmsr(MTRRPhysBase0 + 2*i, mtrr->base);
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wrmsr(MTRRPhysMask0 + 2*i, mtrr->mask);
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}
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static int
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mtrrvcnt(void)
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{
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vlong cap;
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int vcnt;
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rdmsr(MTRRCap, &cap);
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vcnt = cap & Capvcnt;
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if(vcnt > Nmtrr)
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vcnt = Nmtrr;
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return vcnt;
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}
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static int
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mtrrgetall(void)
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{
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int i, vcnt;
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vcnt = mtrrvcnt();
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for(i = 0; i < vcnt; i++)
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mtrrget(&mtrreg[i], i);
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return vcnt;
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}
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static void
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mtrrputall(void)
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{
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int s, i, vcnt;
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ulong cr0, cr4;
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vlong def;
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int i, x;
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s = splhi();
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x = splhi();
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cr4 = getcr4();
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putcr4(cr4 & ~CR4PageGlobalEnable);
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/* disable cache */
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cr0 = getcr0();
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wbinvd();
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putcr0(cr0 | CR0CacheDisable);
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wbinvd();
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rdmsr(MTRRDefaultType, &def);
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wrmsr(MTRRDefaultType, def & ~(vlong)Defena);
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vcnt = mtrrvcnt();
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for(i=0; i<vcnt; i++)
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mtrrput(&mtrreg[i], i);
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/* disable PGE */
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cr4 = getcr4();
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putcr4(cr4 & ~CR4PageGlobalEnable);
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/* flush tlb */
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putcr3(getcr3());
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/* disable MTRRs */
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wrmsr(MTRRDefaultType, s->def & ~(vlong)(Defena|Deffixena|Deftype));
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wbinvd();
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wrmsr(MTRRDefaultType, def);
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/* write all registers */
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if(s->cap & Capfix){
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for(i = 0; i < nelem(fixreg); i++)
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wrmsr(fixreg[i].msr, s->fixreg[i]);
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}
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for(i = 0; i < s->nvarreg; i++){
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wrmsr(MTRRPhysBase0 + 2*i, s->varreg[i].base);
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wrmsr(MTRRPhysMask0 + 2*i, s->varreg[i].mask);
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}
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||||
/* flush tlb */
|
||||
putcr3(getcr3());
|
||||
|
||||
/* enable MTRRs */
|
||||
wrmsr(MTRRDefaultType, s->def);
|
||||
|
||||
/* reenable cache */
|
||||
putcr0(cr0);
|
||||
|
||||
/* reenable PGE */
|
||||
putcr4(cr4);
|
||||
|
||||
splx(s);
|
||||
splx(x);
|
||||
}
|
||||
|
||||
static int
|
||||
fls64(uvlong x)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = 0; i < 64; i++)
|
||||
if(x & (1ULL<<i))
|
||||
break;
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
fms64(uvlong x)
|
||||
{
|
||||
int i;
|
||||
|
||||
if(x == 0)
|
||||
return 0;
|
||||
for(i = 63; i >= 0; i--)
|
||||
if(x & (1ULL<<i))
|
||||
break;
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
range2varreg(State *s, Range r, int index, int doit)
|
||||
{
|
||||
uvlong len;
|
||||
|
||||
if(index < 0)
|
||||
return -1;
|
||||
|
||||
if(r.base <= 0x100000 && (s->def & Deffixena) != 0){
|
||||
r.size += r.base;
|
||||
r.base = 0;
|
||||
}
|
||||
|
||||
if(r.base >= 0x100000000ULL && r.base <= s->tom2){
|
||||
if(r.base + r.size <= s->tom2){
|
||||
if(r.type != Writeback)
|
||||
return -1;
|
||||
return index;
|
||||
}
|
||||
}
|
||||
|
||||
len = r.size;
|
||||
while(len){
|
||||
if(index >= s->nvarreg)
|
||||
return -1;
|
||||
if(fls64(r.base) > fms64(len))
|
||||
r.size = 1ULL << fms64(len);
|
||||
else
|
||||
r.size = 1ULL << fls64(r.base);
|
||||
if(doit)
|
||||
setvarreg(s, &r, index);
|
||||
index++;
|
||||
len -= r.size;
|
||||
r.base += r.size;
|
||||
}
|
||||
return index;
|
||||
}
|
||||
|
||||
static int ranges2varregs(State*, Range*, int, int, int);
|
||||
|
||||
/*
|
||||
* try to combine same type ranges that are split by
|
||||
* higher precedence ranges.
|
||||
*/
|
||||
static int
|
||||
ranges2varregscomb(State *s, Range *rp, int nr, int index, int doit)
|
||||
{
|
||||
Range rr;
|
||||
int i, j;
|
||||
|
||||
if(nr < 2 || rp[0].type == rp[1].type)
|
||||
return -1;
|
||||
rr = rp[0];
|
||||
if(preftype(rr.type, rp[1].type) == rr.type)
|
||||
rr.type = rp[1].type;
|
||||
for(j = 1; j < nr; j++){
|
||||
if(rp[j].type != rr.type
|
||||
&& preftype(rp[j].type, rr.type) != rp[j].type)
|
||||
return -1;
|
||||
rr.size += rp[j].size;
|
||||
}
|
||||
i = ranges2varregs(s, &rr, 1, index, doit);
|
||||
for(j = 0; j < nr && i >= index; j++){
|
||||
if(rp[j].type != rr.type)
|
||||
i = range2varreg(s, rp[j], i, doit);
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
ranges2varregs(State *s, Range *rp, int nr, int index, int doit)
|
||||
{
|
||||
int i, j, k;
|
||||
|
||||
if(nr == 1){
|
||||
if(rp->type == (s->def & Deftype))
|
||||
return index;
|
||||
return range2varreg(s, *rp, index, doit);
|
||||
}
|
||||
|
||||
/* try combining */
|
||||
i = ranges2varregscomb(s, rp, nr, index, doit);
|
||||
|
||||
/*
|
||||
* now see if we can find a better solution using
|
||||
* different splittings.
|
||||
*/
|
||||
for(k = 1; k < nr; k++){
|
||||
j = ranges2varregs(s, rp+k, nr-k,
|
||||
ranges2varregs(s, rp, k, index, 0), 0);
|
||||
if(j < 0)
|
||||
continue;
|
||||
if(i < 0 || j < i)
|
||||
i = doit ? ranges2varregs(s, rp+k, nr-k,
|
||||
ranges2varregs(s, rp, k, index, 1), 1) : j;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
range2fixreg(State *s, Range r)
|
||||
{
|
||||
Range rr;
|
||||
int i;
|
||||
|
||||
for(i = 0; i < Nfixreg; i++){
|
||||
if(!getfixreg(s, &rr, i) || rr.base + rr.size <= r.base)
|
||||
continue;
|
||||
if(rr.base >= r.base + r.size)
|
||||
break;
|
||||
if(r.base > rr.base || r.base + r.size < rr.base + rr.size)
|
||||
return -1;
|
||||
rr.type = r.type;
|
||||
setfixreg(s, &rr, i);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
setranges(State *s, Range *rp, int nr)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
if(nr < 1 || nr > Nranges)
|
||||
return -1;
|
||||
|
||||
s->def &= ~(vlong)(Defena|Deffixena|Deftype);
|
||||
|
||||
i = 0;
|
||||
if(rp[0].size != s->mask+1 || rp[0].type != Uncacheable){
|
||||
s->def |= Defena;
|
||||
|
||||
/* first handle ranges below 1MB using fixed registers */
|
||||
if(rp[0].size < 0x100000 && (s->cap & Capfix) != 0){
|
||||
s->def |= Deffixena;
|
||||
|
||||
for(i = 0; i < Nfixreg; i++)
|
||||
setfixreg(s, nil, i);
|
||||
|
||||
while(nr > 0 && rp->base < 0x100000){
|
||||
if(range2fixreg(s, *rp) < 0)
|
||||
return -1;
|
||||
if(rp->base + rp->size > 0x100000)
|
||||
break;
|
||||
rp++;
|
||||
nr--;
|
||||
}
|
||||
}
|
||||
|
||||
/* remaining ranges to to variable registers */
|
||||
if(nr > 0){
|
||||
/* make sure the algorithm doesnt explode */
|
||||
if(nr > Nvarreg+1)
|
||||
return -1;
|
||||
|
||||
/* try with UC default type */
|
||||
s->def = (s->def & ~(vlong)Deftype) | Uncacheable;
|
||||
i = ranges2varregs(s, rp, nr, 0, 1);
|
||||
|
||||
/* try with WB default type, dont do it yet */
|
||||
s->def = (s->def & ~(vlong)Deftype) | Writeback;
|
||||
j = ranges2varregs(s, rp, nr, 0, 0);
|
||||
if(j < 0 || (i >= 0 && i <= j)){
|
||||
/* WB not better or worse, use UC solution */
|
||||
s->def = (s->def & ~(vlong)Deftype) | Uncacheable;
|
||||
} else {
|
||||
/* WB default is better, doit! */
|
||||
i = ranges2varregs(s, rp, nr, 0, 1);
|
||||
}
|
||||
if(i < 0)
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear unused variable registers */
|
||||
for(; i < s->nvarreg; i++)
|
||||
setvarreg(s, nil, i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
checkranges(State *s, Range *rp, int nr)
|
||||
{
|
||||
uvlong base, next;
|
||||
int i;
|
||||
|
||||
for(i = 0; i < nr; i++){
|
||||
next = rp[i].base + rp[i].size;
|
||||
for(base = rp[i].base; base < next; base = getnext(s, base, nil)){
|
||||
if(gettype(s, base, nil) != rp[i].type)
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
getranges(State *s, Range *rp, int nr, Range *new)
|
||||
{
|
||||
uvlong base, next;
|
||||
Range *rs, *re;
|
||||
int type;
|
||||
|
||||
rs = rp;
|
||||
re = rp + nr;
|
||||
for(base = 0; base <= s->mask; base = next) {
|
||||
if(rp >= re)
|
||||
return -1;
|
||||
type = gettype(s, base, new);
|
||||
next = getnext(s, base, new);
|
||||
while(next <= s->mask && (gettype(s, next, new) == type))
|
||||
next = getnext(s, next, new);
|
||||
rp->base = base;
|
||||
rp->size = next - base;
|
||||
rp->type = type;
|
||||
rp++;
|
||||
}
|
||||
return rp - rs;
|
||||
}
|
||||
|
||||
static int dosync;
|
||||
static QLock mtrrlk;
|
||||
static State cpu0state;
|
||||
static Range ranges[Nranges];
|
||||
|
||||
char*
|
||||
mtrr(uvlong base, uvlong size, char *tstr)
|
||||
{
|
||||
static State newstate;
|
||||
Range new;
|
||||
int nr;
|
||||
|
||||
if(cpu0state.mask == 0)
|
||||
return "mtrr not supported";
|
||||
|
||||
if(size < 0x1000)
|
||||
return "size too small";
|
||||
if((base | size) & 0xFFF)
|
||||
return "base or size not page aligned";
|
||||
if(base & ~cpu0state.mask)
|
||||
return "base out of range";
|
||||
if(base + size > cpu0state.mask+1)
|
||||
return "size out of range";
|
||||
|
||||
new.base = base;
|
||||
new.size = size;
|
||||
if((new.type = str2type(tstr)) < 0)
|
||||
return "bad cache type";
|
||||
|
||||
qlock(&mtrrlk);
|
||||
newstate = cpu0state;
|
||||
nr = getranges(&newstate, ranges, Nranges, &new);
|
||||
if(setranges(&newstate, ranges, nr) < 0
|
||||
|| checkranges(&newstate, ranges, nr) < 0){
|
||||
qunlock(&mtrrlk);
|
||||
return "cache range not satisfiable";
|
||||
}
|
||||
cpu0state = newstate;
|
||||
coherence();
|
||||
dosync = 1;
|
||||
mtrrclock();
|
||||
qunlock(&mtrrlk);
|
||||
|
||||
return nil;
|
||||
}
|
||||
|
||||
int
|
||||
mtrrprint(char *buf, long bufsize)
|
||||
{
|
||||
char *cp, *ep;
|
||||
int i, nr;
|
||||
|
||||
if(cpu0state.mask == 0)
|
||||
return 0;
|
||||
|
||||
cp = buf;
|
||||
ep = buf + bufsize;
|
||||
|
||||
qlock(&mtrrlk);
|
||||
nr = getranges(&cpu0state, ranges, Nranges, nil);
|
||||
for(i = 0; i < nr; i++){
|
||||
cp = seprint(cp, ep, "cache %#.16llux %15llud %s\n",
|
||||
ranges[i].base,
|
||||
ranges[i].size,
|
||||
type2str(ranges[i].type));
|
||||
}
|
||||
qunlock(&mtrrlk);
|
||||
|
||||
return cp - buf;
|
||||
}
|
||||
|
||||
/* called from clock interrupt */
|
||||
void
|
||||
mtrrclock(void) /* called from clock interrupt */
|
||||
mtrrclock(void)
|
||||
{
|
||||
static Ref bar1, bar2;
|
||||
int s;
|
||||
int x;
|
||||
|
||||
if(dosync == 0)
|
||||
if(dosync == 0 || cpu0state.mask == 0)
|
||||
return;
|
||||
|
||||
s = splhi();
|
||||
x = splhi();
|
||||
|
||||
/*
|
||||
* wait for all CPUs to sync here, so that the MTRR setup gets
|
||||
|
|
@ -233,7 +736,7 @@ mtrrclock(void) /* called from clock interrupt */
|
|||
while(bar1.ref < conf.nmach)
|
||||
microdelay(10);
|
||||
|
||||
mtrrputall();
|
||||
putstate(&cpu0state);
|
||||
|
||||
/*
|
||||
* wait for all CPUs to sync up again, so that we don't continue
|
||||
|
|
@ -248,128 +751,21 @@ mtrrclock(void) /* called from clock interrupt */
|
|||
decref(&bar2);
|
||||
|
||||
dosync = 0;
|
||||
splx(s);
|
||||
}
|
||||
|
||||
static char*
|
||||
mtrr0(uvlong base, uvlong size, char *tstr)
|
||||
{
|
||||
int i, vcnt, slot, type, mtype, mok;
|
||||
vlong def, cap;
|
||||
uvlong mp, msize;
|
||||
|
||||
if(!(m->cpuiddx & Mtrr))
|
||||
return "mtrrs not supported";
|
||||
if(base & (BY2PG-1) || size & (BY2PG-1) || size == 0)
|
||||
return "mtrr base or size not 4k aligned or zero size";
|
||||
if(!ispow2(size))
|
||||
return "mtrr size not power of 2";
|
||||
if(base & (size - 1))
|
||||
return "mtrr base not naturally aligned";
|
||||
|
||||
if((type = str2type(tstr)) == -1)
|
||||
return "mtrr bad type";
|
||||
|
||||
rdmsr(MTRRCap, &cap);
|
||||
rdmsr(MTRRDefaultType, &def);
|
||||
|
||||
switch(type){
|
||||
default:
|
||||
return "mtrr unknown type";
|
||||
case Writecomb:
|
||||
if(!(cap & Capwc))
|
||||
return "mtrr type wc (write combining) unsupported";
|
||||
/* fallthrough */
|
||||
case Uncacheable:
|
||||
case Writethru:
|
||||
case Writeprot:
|
||||
case Writeback:
|
||||
break;
|
||||
}
|
||||
|
||||
vcnt = mtrrgetall();
|
||||
|
||||
slot = -1;
|
||||
for(i = 0; i < vcnt; i++){
|
||||
mok = mtrrdec(&mtrreg[i], &mp, &msize, &mtype);
|
||||
if(slot == -1 && !mok)
|
||||
slot = i; /* good, but look further for exact match */
|
||||
if(mok && mp == base && msize == size){
|
||||
slot = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(slot == -1)
|
||||
return "no free mtrr slots";
|
||||
|
||||
mtrrenc(&mtrreg[slot], base, size, type, 1);
|
||||
|
||||
coherence();
|
||||
|
||||
dosync = 1;
|
||||
mtrrclock();
|
||||
|
||||
return nil;
|
||||
}
|
||||
|
||||
char*
|
||||
mtrr(uvlong base, uvlong size, char *tstr)
|
||||
{
|
||||
static QLock mtrrlk;
|
||||
char *err;
|
||||
|
||||
qlock(&mtrrlk);
|
||||
err = mtrr0(base, size, tstr);
|
||||
qunlock(&mtrrlk);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int
|
||||
mtrrprint(char *buf, long bufsize)
|
||||
{
|
||||
int i, n, vcnt, type;
|
||||
uvlong base, size;
|
||||
Mtrreg mtrr;
|
||||
vlong def;
|
||||
|
||||
if(!(m->cpuiddx & Mtrr))
|
||||
return 0;
|
||||
rdmsr(MTRRDefaultType, &def);
|
||||
n = snprint(buf, bufsize, "cache default %s\n",
|
||||
type2str(def & Deftype));
|
||||
vcnt = mtrrvcnt();
|
||||
for(i = 0; i < vcnt; i++){
|
||||
mtrrget(&mtrr, i);
|
||||
if (mtrrdec(&mtrr, &base, &size, &type))
|
||||
n += snprint(buf+n, bufsize-n,
|
||||
"cache 0x%llux %llud %s\n",
|
||||
base, size, type2str(type));
|
||||
}
|
||||
return n;
|
||||
splx(x);
|
||||
}
|
||||
|
||||
/* called from cpuidentify() */
|
||||
void
|
||||
mtrrsync(void)
|
||||
{
|
||||
static vlong cap0, def0;
|
||||
vlong cap, def;
|
||||
State s;
|
||||
|
||||
rdmsr(MTRRCap, &cap);
|
||||
rdmsr(MTRRDefaultType, &def);
|
||||
|
||||
if(m->machno == 0){
|
||||
cap0 = cap;
|
||||
def0 = def;
|
||||
mtrrgetall();
|
||||
if(getstate(&s) < 0)
|
||||
return;
|
||||
if(cpu0state.mask == 0){
|
||||
cpu0state = s;
|
||||
coherence();
|
||||
return;
|
||||
}
|
||||
|
||||
if(cap0 != cap)
|
||||
print("mtrrcap%d: %lluX %lluX\n",
|
||||
m->machno, cap0, cap);
|
||||
if(def0 != def)
|
||||
print("mtrrdef%d: %lluX %lluX\n",
|
||||
m->machno, def0, def);
|
||||
mtrrputall();
|
||||
putstate(&cpu0state);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue