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bcm64: no need to flush instruction cache when switching TTBR0

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This commit is contained in:
cinap_lenrek 2019-05-17 18:56:34 +02:00
parent 5c5c1b6666
commit 2235660f86
1 changed files with 1 additions and 2 deletions
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3
sys/src/9/bcm64/l.s
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@ -331,8 +331,7 @@ TEXT setttbr(SB), 1, $-4
MSR R0, TTBR0_EL1
DSB $ISH
ISB $SY
B cacheiinv(SB)
RETURN
/*
* TLB maintenance operations.