ether8169: huge cleanup, remove magic stuff
This commit is contained in:
cinap_lenrek
parent
e113f037a3
commit
203443ee05
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@ -165,6 +165,8 @@ enum { /* Phystatus */
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};
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enum { /* Cplusc */
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Txenb = 0x0001, /* enable C+ transmit mode */
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Rxenb = 0x0002, /* enable C+ receive mode */
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Mulrw = 0x0008, /* PCI Multiple R/W Enable */
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Dac = 0x0010, /* PCI Dual Address Cycle Enable */
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Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
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@ -222,7 +224,6 @@ enum { /* Ring sizes (<= 1024) */
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Mtu = ETHERMAXTU,
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Mps = ROUNDUP(ETHERMAXTU+4, 128),
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// Mps = Mtu + 8 + 14, /* if(mtu>ETHERMAXTU) */
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};
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typedef struct Dtcc Dtcc;
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@ -252,13 +253,14 @@ enum { /* Variants */
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typedef struct Ctlr Ctlr;
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typedef struct Ctlr {
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Lock;
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int port;
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Pcidev* pcidev;
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Ctlr* next;
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int active;
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QLock alock; /* attach */
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Lock ilock; /* init */
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int init; /* */
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Rendez reset;
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@ -271,26 +273,21 @@ typedef struct Ctlr {
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Mii* mii;
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Lock tlock; /* transmit */
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D* td; /* descriptor ring */
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Block** tb; /* transmit buffers */
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int ntd;
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int tdh; /* head - producer index (host) */
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int tdt; /* tail - consumer index (NIC) */
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int ntdfree;
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int ntq;
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// int rbsz; /* receive buffer size */
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Lock rlock; /* receive */
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D* rd; /* descriptor ring */
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Block** rb; /* receive buffers */
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int nrd;
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int rdh; /* head - producer index (NIC) */
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int rdt; /* tail - consumer index (host) */
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int nrdfree;
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int nrq;
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int tcr; /* transmit configuration register */
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int rcr; /* receive configuration register */
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@ -303,10 +300,11 @@ typedef struct Ctlr {
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uint udpf;
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uint ipf;
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uint fovf;
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uint ierrs;
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uint rer;
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uint rdu;
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uint punlc;
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uint serr;
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uint fovw;
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uint mcast;
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uint frag; /* partial packets; rb was too small */
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} Ctlr;
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@ -400,7 +398,7 @@ rtl8169mii(Ctlr* ctlr)
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ctlr->mii = nil;
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return -1;
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}
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print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
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print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
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phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
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miiane(ctlr->mii, ~0, ~0, ~0);
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@ -416,14 +414,13 @@ rtl8169promiscuous(void* arg, int on)
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edev = arg;
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ctlr = edev->ctlr;
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ilock(&ctlr->ilock);
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ilock(ctlr);
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if(on)
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ctlr->rcr |= Aap;
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else
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ctlr->rcr &= ~Aap;
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csr32w(ctlr, Rcr, ctlr->rcr);
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iunlock(&ctlr->ilock);
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iunlock(ctlr);
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}
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enum {
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@ -470,7 +467,7 @@ rtl8169multicast(void* ether, uchar *eaddr, int add)
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edev = ether;
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ctlr = edev->ctlr;
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ilock(&ctlr->ilock);
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ilock(ctlr);
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ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
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@ -486,7 +483,7 @@ rtl8169multicast(void* ether, uchar *eaddr, int add)
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csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
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}
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iunlock(&ctlr->ilock);
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iunlock(ctlr);
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}
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static long
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@ -547,12 +544,14 @@ rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
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l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
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l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
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l += snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
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l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
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l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
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l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
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l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
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l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
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l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
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l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
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l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
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l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
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l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
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@ -616,33 +615,26 @@ static void
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rtl8169replenish(Ctlr* ctlr)
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{
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D *d;
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int rdt;
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int x;
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Block *bp;
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rdt = ctlr->rdt;
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while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
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d = &ctlr->rd[rdt];
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if(ctlr->rb[rdt] == nil){
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/*
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* Simple allocation for now.
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* This better be aligned on 8.
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*/
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bp = iallocb(Mps);
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if(bp == nil){
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iprint("no available buffers\n");
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break;
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}
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ctlr->rb[rdt] = bp;
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d->addrlo = PCIWADDR(bp->rp);
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d->addrhi = 0;
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coherence();
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}else
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iprint("i8169: rx overrun\n");
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d->control |= Own|Mps;
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rdt = NEXT(rdt, ctlr->nrd);
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ctlr->nrdfree++;
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x = ctlr->rdt;
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while(NEXT(x, ctlr->nrd) != ctlr->rdh){
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bp = iallocb(Mps);
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if(bp == nil){
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iprint("rtl8169: no available buffers\n");
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break;
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}
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ctlr->rb[x] = bp;
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ctlr->nrq++;
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d = &ctlr->rd[x];
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d->addrlo = PCIWADDR(bp->rp);
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d->addrhi = 0;
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coherence();
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d->control = (d->control & Eor) | Own | BALLOC(bp);
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x = NEXT(x, ctlr->nrd);
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ctlr->rdt = x;
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}
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ctlr->rdt = rdt;
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}
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static int
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@ -655,159 +647,66 @@ rtl8169init(Ether* edev)
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u8int cplusc;
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ctlr = edev->ctlr;
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ilock(&ctlr->ilock);
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ilock(ctlr);
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rtl8169halt(ctlr);
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rtl8169reset(ctlr);
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/*
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* MAC Address is not settable on some (all?) chips.
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* Must put chip into config register write enable mode.
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*/
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csr8w(ctlr, Cr9346, Eem1|Eem0);
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/*
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* Transmitter.
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*/
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memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
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ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
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ctlr->td[ctlr->ntd-1].control = Eor;
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for(i = 0; i < ctlr->ntd; i++)
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if(bp = ctlr->tb[i]){
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ctlr->tb[i] = nil;
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freeb(bp);
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}
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/*
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* Receiver.
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* Need to do something here about the multicast filter.
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*/
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memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
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ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
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ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
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ctlr->rd[ctlr->nrd-1].control = Eor;
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for(i = 0; i < ctlr->nrd; i++)
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if((bp = ctlr->rb[i]) != nil){
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if(bp = ctlr->rb[i]){
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ctlr->rb[i] = nil;
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freeb(bp);
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}
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rtl8169replenish(ctlr);
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ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
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/*
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* Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
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* settings in Tcr/Rcr; the (1<<14) is magic.
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*/
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cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
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cplusc |= /*Rxchksum|*/Mulrw;
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switch(ctlr->macv){
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default:
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panic("ether8169: unknown macv %#08ux for vid %#ux did %#ux",
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ctlr->macv, ctlr->pcidev->vid, ctlr->pcidev->did);
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case Macv01:
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break;
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case Macv02:
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case Macv03:
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cplusc |= 1<<14; /* magic */
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break;
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case Macv05:
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/*
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* This is interpreted from clearly bogus code
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* in the manufacturer-supplied driver, it could
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* be wrong. Untested.
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*/
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r = csr8r(ctlr, Config2) & 0x07;
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if(r == 0x01) /* 66MHz PCI */
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csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
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else
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csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
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pciclrmwi(ctlr->pcidev);
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break;
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case Macv13:
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/*
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* This is interpreted from clearly bogus code
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* in the manufacturer-supplied driver, it could
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* be wrong. Untested.
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*/
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pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */
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pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */
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break;
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case Macv04:
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case Macv07:
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case Macv07a:
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case Macv11:
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case Macv12:
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case Macv12a:
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case Macv14:
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case Macv15:
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case Macv25:
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break;
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}
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cplusc = csr16r(ctlr, Cplusc);
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cplusc &= ~(Endian|Rxchksum);
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cplusc |= Txenb|Rxenb|Mulrw;
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csr16w(ctlr, Cplusc, cplusc);
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/*
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* Enable receiver/transmitter.
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* Need to do this first or some of the settings below
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* won't take.
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*/
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switch(ctlr->pciv){
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default:
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csr8w(ctlr, Cr, Te|Re);
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csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
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csr32w(ctlr, Rcr, ctlr->rcr);
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csr32w(ctlr, Mar0, 0);
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csr32w(ctlr, Mar0+4, 0);
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ctlr->mchash = 0;
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case Rtl8169sc:
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case Rtl8168b:
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break;
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}
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/*
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* Interrupts.
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*/
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csr32w(ctlr, Timerint, 0);
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ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
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csr16w(ctlr, Imr, ctlr->imr);
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/*
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* Clear missed-packet counter;
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* clear early transmit threshold value;
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* set the descriptor ring base addresses;
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* set the maximum receive packet size;
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* no early-receive interrupts.
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*
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* note: the maximum rx size is a filter. the size of the buffer
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* in the descriptor ring is still honored. we will toss >Mtu
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* packets because they've been fragmented into multiple
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* rx buffers.
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*/
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csr32w(ctlr, Mpc, 0);
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csr8w(ctlr, Etx, 0x3f); /* magic */
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csr32w(ctlr, Tnpds+4, 0);
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csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
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csr32w(ctlr, Rdsar+4, 0);
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csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
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csr16w(ctlr, Rms, 16383); /* was Mps; see above comment */
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r = csr16r(ctlr, Mulint) & 0xF000; /* no early rx interrupts */
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csr16w(ctlr, Mulint, r);
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csr16w(ctlr, Cplusc, cplusc);
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csr8w(ctlr, Cr, Te|Re);
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csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
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ctlr->tcr = csr32r(ctlr, Tcr);
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ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
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ctlr->mchash = 0;
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csr32w(ctlr, Mar0, 0);
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csr32w(ctlr, Mar0+4, 0);
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csr32w(ctlr, Rcr, ctlr->rcr);
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/* maximum packet sizes, unlimited */
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csr8w(ctlr, Etx, 0x3f);
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csr16w(ctlr, Rms, 0x3fff);
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csr16w(ctlr, Coal, 0);
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/*
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* Set configuration.
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*/
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switch(ctlr->pciv){
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case Rtl8169sc:
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csr8w(ctlr, Cr, Te|Re);
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csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
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csr32w(ctlr, Rcr, ctlr->rcr);
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break;
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case Rtl8168b:
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case Rtl8169c:
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csr16w(ctlr, Cplusc, 0x2000); /* magic */
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csr8w(ctlr, Cr, Te|Re);
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csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
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csr32w(ctlr, Rcr, ctlr->rcr);
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break;
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}
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ctlr->tcr = csr32r(ctlr, Tcr);
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csr8w(ctlr, Cr9346, 0);
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/* no early rx interrupts */
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r = csr16r(ctlr, Mulint) & 0xF000;
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csr16w(ctlr, Mulint, r);
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iunlock(&ctlr->ilock);
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ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
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csr16w(ctlr, Imr, ctlr->imr);
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csr32w(ctlr, Mpc, 0);
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iunlock(ctlr);
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return 0;
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}
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@ -819,11 +718,11 @@ rtl8169reseter(void *arg)
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Ctlr *ctlr;
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edev = arg;
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ctlr = edev->ctlr;
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for(;;){
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print("rtl8169: reset\n");
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rtl8169init(edev);
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ctlr = edev->ctlr;
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qunlock(&ctlr->alock);
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while(waserror())
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@ -843,10 +742,7 @@ rtl8169attach(Ether* edev)
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ctlr = edev->ctlr;
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qlock(&ctlr->alock);
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if(ctlr->init == 0){
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/*
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* Handle allocation/init errors here.
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*/
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if(ctlr->init++ == 0){
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ctlr->td = mallocalign(sizeof(D)*Ntd, 256, 0, 0);
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ctlr->tb = malloc(Ntd*sizeof(Block*));
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ctlr->ntd = Ntd;
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@ -854,10 +750,9 @@ rtl8169attach(Ether* edev)
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ctlr->rb = malloc(Nrd*sizeof(Block*));
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ctlr->nrd = Nrd;
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ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
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ctlr->init = 1;
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kproc("rtl8169", rtl8169reseter, edev);
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qlock(&ctlr->alock); /* reset proc unlocks when finished */
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qlock(&ctlr->alock);
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}
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qunlock(&ctlr->alock);
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@ -913,7 +808,8 @@ rtl8169transmit(Ether* edev)
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ctlr = edev->ctlr;
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ilock(&ctlr->tlock);
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if(!canlock(ctlr))
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return;
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for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
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d = &ctlr->td[x];
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if(d->control & Own)
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@ -927,7 +823,6 @@ rtl8169transmit(Ether* edev)
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*/
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freeb(ctlr->tb[x]);
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ctlr->tb[x] = nil;
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ctlr->ntq--;
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}
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ctlr->tdh = x;
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@ -941,11 +836,12 @@ rtl8169transmit(Ether* edev)
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d->addrlo = PCIWADDR(bp->rp);
|
||||
d->addrhi = 0;
|
||||
coherence();
|
||||
ctlr->tb[x] = bp;
|
||||
d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
|
||||
|
||||
x = NEXT(x, ctlr->ntd);
|
||||
ctlr->tb[x] = bp;
|
||||
ctlr->ntq++;
|
||||
|
||||
x = NEXT(x, ctlr->ntd);
|
||||
}
|
||||
if(x != ctlr->tdt)
|
||||
ctlr->tdt = x;
|
||||
|
|
@ -956,31 +852,36 @@ rtl8169transmit(Ether* edev)
|
|||
coherence();
|
||||
csr8w(ctlr, Tppoll, Npq);
|
||||
}
|
||||
|
||||
iunlock(&ctlr->tlock);
|
||||
unlock(ctlr);
|
||||
}
|
||||
|
||||
static void
|
||||
rtl8169receive(Ether* edev)
|
||||
{
|
||||
D *d;
|
||||
int rdh;
|
||||
Block *bp;
|
||||
Ctlr *ctlr;
|
||||
u32int control;
|
||||
int x;
|
||||
|
||||
ctlr = edev->ctlr;
|
||||
|
||||
rdh = ctlr->rdh;
|
||||
x = ctlr->rdh;
|
||||
for(;;){
|
||||
d = &ctlr->rd[rdh];
|
||||
|
||||
if(d->control & Own)
|
||||
d = &ctlr->rd[x];
|
||||
if((control = d->control) & Own)
|
||||
break;
|
||||
|
||||
control = d->control;
|
||||
bp = ctlr->rb[x];
|
||||
ctlr->rb[x] = nil;
|
||||
ctlr->nrq--;
|
||||
|
||||
x = NEXT(x, ctlr->nrd);
|
||||
ctlr->rdh = x;
|
||||
|
||||
if(ctlr->nrq < ctlr->nrd/2)
|
||||
rtl8169replenish(ctlr);
|
||||
|
||||
if((control & (Fs|Ls|Res)) == (Fs|Ls)){
|
||||
bp = ctlr->rb[rdh];
|
||||
bp->wp = bp->rp + (control & RxflMASK) - 4;
|
||||
|
||||
if(control & Fovf)
|
||||
|
|
@ -1017,37 +918,17 @@ rtl8169receive(Ether* edev)
|
|||
}else{
|
||||
if(!(control & Res))
|
||||
ctlr->frag++;
|
||||
/* iprint("i8169: control %#.8ux\n", control); */
|
||||
freeb(ctlr->rb[rdh]);
|
||||
freeb(bp);
|
||||
}
|
||||
ctlr->rb[rdh] = nil;
|
||||
d->control &= Eor;
|
||||
ctlr->nrdfree--;
|
||||
rdh = NEXT(rdh, ctlr->nrd);
|
||||
|
||||
if(ctlr->nrdfree < ctlr->nrd/2)
|
||||
rtl8169replenish(ctlr);
|
||||
}
|
||||
ctlr->rdh = rdh;
|
||||
}
|
||||
|
||||
static void
|
||||
rtl8169restart(Ctlr *ctlr)
|
||||
{
|
||||
ilock(&ctlr->ilock);
|
||||
|
||||
/* disable interrupts */
|
||||
ctlr->imr = 0;
|
||||
csr16w(ctlr, Imr, ctlr->imr);
|
||||
csr16w(ctlr, Isr, 0xFFFF);
|
||||
|
||||
/* software reset */
|
||||
csr8w(ctlr, Cr, Rst);
|
||||
csr8r(ctlr, Cr);
|
||||
|
||||
rtl8169halt(ctlr);
|
||||
wakeup(&ctlr->reset);
|
||||
|
||||
iunlock(&ctlr->ilock);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -1065,40 +946,30 @@ rtl8169interrupt(Ureg*, void* arg)
|
|||
if((isr & ctlr->imr) == 0)
|
||||
break;
|
||||
|
||||
if(isr & Fovw){
|
||||
if(isr & Serr)
|
||||
ctlr->serr++;
|
||||
if(isr & Fovw)
|
||||
ctlr->fovw++;
|
||||
if(isr & Rer)
|
||||
ctlr->rer++;
|
||||
if(isr & Rdu)
|
||||
ctlr->rdu++;
|
||||
if(isr & Punlc)
|
||||
ctlr->punlc++;
|
||||
|
||||
if(isr & (Serr|Fovw)){
|
||||
rtl8169restart(ctlr);
|
||||
break;
|
||||
}
|
||||
|
||||
if(isr & (Punlc|Rdu|Rer|Rok)){
|
||||
if(isr & (Punlc|Rdu|Rer|Rok))
|
||||
rtl8169receive(edev);
|
||||
if(!(isr & (Punlc|Rok)))
|
||||
ctlr->ierrs++;
|
||||
if(isr & Rer)
|
||||
ctlr->rer++;
|
||||
if(isr & Rdu)
|
||||
ctlr->rdu++;
|
||||
if(isr & Punlc)
|
||||
ctlr->punlc++;
|
||||
isr &= ~(Rdu|Rer|Rok);
|
||||
}
|
||||
|
||||
if(isr & (Tdu|Ter|Tok)){
|
||||
if(isr & (Tdu|Ter|Tok))
|
||||
rtl8169transmit(edev);
|
||||
isr &= ~(Tdu|Ter|Tok);
|
||||
}
|
||||
|
||||
if(isr & Punlc){
|
||||
if(isr & Punlc)
|
||||
rtl8169link(edev);
|
||||
isr &= ~Punlc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Some of the reserved bits get set sometimes...
|
||||
*/
|
||||
if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
|
||||
panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux",
|
||||
csr16r(ctlr, Imr), isr);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1190,6 +1061,7 @@ rtl8169pci(void)
|
|||
if(rtl8169reset(ctlr)){
|
||||
iofree(port);
|
||||
free(ctlr);
|
||||
print("rtl8169: reset failed\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -1270,7 +1142,6 @@ rtl8169pnp(Ether* edev)
|
|||
edev->arg = edev;
|
||||
edev->promiscuous = rtl8169promiscuous;
|
||||
edev->multicast = rtl8169multicast;
|
||||
// edev->shutdown = rtl8169shutdown;
|
||||
|
||||
rtl8169link(edev);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue