games/snes: cpu timing fix
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b13425e2b0
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0d080855b2
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@ -609,11 +609,8 @@ enum { COP = 0, BRK = 1, NMI = 3, IRQ = 5 };
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static void
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static void
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interrupt(int src)
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interrupt(int src)
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{
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{
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if(src > BRK){
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if(src > BRK)
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io();
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memread(pc | rPB);
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if(!emu)
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io();
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}
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if(!emu)
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if(!emu)
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push8(rPB >> 16);
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push8(rPB >> 16);
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push16(pc);
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push16(pc);
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@ -687,7 +684,6 @@ cpustep(void)
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lastpc = curpc;
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lastpc = curpc;
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if(trace)
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if(trace)
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print("%.6x %.2x A=%.4x X=%.4x Y=%.4x P=%.2x %.2x\n", curpc, op, rA, rX, rY, rP, rS);
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print("%.6x %.2x A=%.4x X=%.4x Y=%.4x P=%.2x %.2x\n", curpc, op, rA, rX, rY, rP, rS);
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cyc = 0;
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switch(op){
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switch(op){
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case 0x00: fetch8(); interrupt(BRK); break;
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case 0x00: fetch8(); interrupt(BRK); break;
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case 0x01: nz(rA |= mem816(dpi(0, 1, 0), 0)); break;
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case 0x01: nz(rA |= mem816(dpi(0, 1, 0), 0)); break;
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@ -24,7 +24,7 @@ extern u16int spc;
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extern u8int dspstate;
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extern u8int dspstate;
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extern u16int dspcounter, noise;
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extern u16int dspcounter, noise;
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extern int ppuclock, spcclock, dspclock, stimerclock;
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extern int ppuclock, spcclock, dspclock, stimerclock, cpupause;
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extern int battery, saveclock, scale, mouse;
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extern int battery, saveclock, scale, mouse;
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enum {
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enum {
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@ -183,7 +183,7 @@ regread(u16int p)
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reg[OPCTLATCH] &= ~3;
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reg[OPCTLATCH] &= ~3;
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return mdr2 = reg[p] | v | mdr2 & 0x20;
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return mdr2 = reg[p] | v | mdr2 & 0x20;
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case 0x2180:
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case 0x2180:
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v = memread(0x7e0000 | reg[0x2181] | reg[0x2182] << 8 | (reg[0x2183] & 1) << 16);
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v = mem[reg[0x2181] | reg[0x2182] << 8 | (reg[0x2183] & 1) << 16];
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incwram();
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incwram();
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return v;
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return v;
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case 0x4016:
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case 0x4016:
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@ -337,7 +337,7 @@ regwrite(u16int p, u8int v)
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case 0x213e:
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case 0x213e:
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return;
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return;
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case 0x2180:
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case 0x2180:
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memwrite(0x7e0000 | reg[0x2181] | reg[0x2182] << 8 | (reg[0x2183] & 1) << 16, v);
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mem[reg[0x2181] | reg[0x2182] << 8 | (reg[0x2183] & 1) << 16] = v;
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incwram();
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incwram();
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return;
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return;
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case 0x4016:
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case 0x4016:
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@ -857,9 +857,11 @@ ppustep(void)
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pixeldraw(rx, ppuy - 1, ppuy >= yvbl ? 0x31c8 : 0);
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pixeldraw(rx, ppuy - 1, ppuy >= yvbl ? 0x31c8 : 0);
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}
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}
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if(ppux == 134)
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cpupause = 1;
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if(ppux == 0x116 && ppuy <= yvbl)
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if(ppux == 0x116 && ppuy <= yvbl)
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hdma |= reg[0x420c];
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hdma |= reg[0x420c];
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if((reg[NMITIMEN] & HCNTIRQ) != 0 && htime == ppux && ((reg[NMITIMEN] & VCNTIRQ) == 0 || vtime == ppuy))
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if((reg[NMITIMEN] & HCNTIRQ) != 0 && htime+4 == ppux && ((reg[NMITIMEN] & VCNTIRQ) == 0 || vtime == ppuy))
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irq |= IRQPPU;
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irq |= IRQPPU;
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if(++ppux >= 340){
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if(++ppux >= 340){
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ppux = 0;
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ppux = 0;
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@ -11,7 +11,7 @@
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uchar *prg, *sram;
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uchar *prg, *sram;
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int nprg, nsram, hirom, battery;
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int nprg, nsram, hirom, battery;
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int ppuclock, spcclock, dspclock, stimerclock, saveclock, msgclock, paused, perfclock;
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int ppuclock, spcclock, dspclock, stimerclock, saveclock, msgclock, paused, perfclock, cpupause;
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Mousectl *mc;
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Mousectl *mc;
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QLock pauselock;
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QLock pauselock;
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u32int keys;
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u32int keys;
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@ -267,7 +267,11 @@ usage:
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qlock(&pauselock);
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qlock(&pauselock);
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qunlock(&pauselock);
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qunlock(&pauselock);
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}
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}
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t = cpustep();
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if(cpupause){
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t = 40;
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cpupause = 0;
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}else
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t = cpustep();
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spcclock -= t;
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spcclock -= t;
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stimerclock += t;
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stimerclock += t;
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ppuclock += t;
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ppuclock += t;
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