\fILowaddr\fR specifies the lowest address in the region and \fIhighaddr\fR one past the highest address.
The region is mapped to a region of the same size in the global segment \fIsegment\fR (see
.IR segment (3)),
starting at \fIoffset\fR.
The \fIaccess\fR field specifies the permitted types of access using the characters \fLr\fR (read), \fLw\fR (write), \fLx\fR (execute) and \fL-\fR (padding character).
The \fIcache\fR field specifies the cacheability of the region, it must be one of \fLuc\fR, \fLwc\fR, \fLwt\fR, \fLwp\fR and \fLwb\fR (as defined in the Intel SDM).
Some registers (\fLCR0\fR and \fLCR4\fR) are split into three registers, suffixed \fLreal\fR, \fLfake\fR and \fLmask\fR.
In this case, \fLreal\fR corresponds to the bits that affect actual CPU execution, \fLfake\fR corresponds to the bits read back by the guest and the bits set in \fLmask\fR are those "owned" by the host.
The guest is free to modify the bits that it owns (in which case it always has the same value in both \fLreal\fR and \fLfake\fR), but attempting to change a host-owned bit from the status in \fLfake\fR causes a VM exit.
Certain bits are owned by the kernel, which means they are fixed in both \fLmask\fR and \fLreal\fR.
The first column contains the cause of the exit and the second column contains the "exit qualification" field that may contain more details on the exit (see Intel SDM).
The remaining columns come in pairs and contain further info and the values of relevant registers.
.LP
Some notable exit causes are (see kernel source code for a complete list)
.TF ".\fL#\fR\fIexception\fR"
.TP
\fL#\fR\fIexception\fR
Exception of the specified type (e.g. \fL#gp\fR for general protection fault).
The exception \fIexcep\fR is triggered in the virtual CPU.
\fIExcep\fR can either be a named exception (such as \fL#gp\fR, in lower case) or an exception number.
A number may be preeded by \fL#\fR to mark it as an exception, otherwise it is delivered as an interrupt (but always disregarding whether interrupts are enabled).
