2020-01-08 02:35:01 +00:00
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#define UART_BASE 0xFFC02000
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#define MPCORE_BASE 0xFFFEC000
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#define L2_BASE 0xFFFEF000
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#define CLOCKMGR_BASE 0xFFD04000
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2020-01-10 18:49:33 +00:00
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#define EMAC1_BASE 0xFF702000
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#define RESETMGR_BASE 0xFFD05000
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#define SYSMGR_BASE 0xFFD08000
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#define OCRAM 0xFFFF0000
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/*RESETMGR*/
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#define PERMODRST (0x14/4)
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/*SYSMGR*/
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#define FPGA_MODULE (0x28/4)
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2020-01-08 02:35:01 +00:00
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#define HPS_CLK 25
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#define TIMERIRQ 29
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#define UART0IRQ 194
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2020-01-10 18:49:33 +00:00
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#define EMAC1IRQ 152
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2020-01-08 02:35:01 +00:00
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#define LEVEL 0
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#define EDGE 1
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