2020-11-29 16:43:22 +00:00
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/error.h"
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extern int i8259assign(Vctl*);
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extern int i8259irqno(int, int);
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extern void i8259init(void);
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extern int i8259isr(int);
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extern void i8259on(void);
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extern void i8259off(void);
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extern int i8259vecno(int);
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void
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archreset(void)
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{
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i8042reset();
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/*
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* Often the BIOS hangs during restart if a conventional 8042
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* warm-boot sequence is tried. The following is Intel specific and
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* seems to perform a cold-boot, but at least it comes back.
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* And sometimes there is no keyboard...
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*
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* The reset register (0xcf9) is usually in one of the bridge
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* chips. The actual location and sequence could be extracted from
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* ACPI but why bother, this is the end of the line anyway.
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*/
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print("Takes a licking and keeps on ticking...\n");
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*(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
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outb(0xcf9, 0x02);
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outb(0xcf9, 0x06);
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print("can't reset\n");
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for(;;)
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idle();
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}
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2021-01-17 20:21:12 +00:00
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void
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delay(int millisecs)
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{
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millisecs *= m->loopconst;
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if(millisecs <= 0)
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millisecs = 1;
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aamloop(millisecs);
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}
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void
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microdelay(int microsecs)
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{
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microsecs *= m->loopconst;
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microsecs /= 1000;
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if(microsecs <= 0)
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microsecs = 1;
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aamloop(microsecs);
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}
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/*
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* performance measurement ticks. must be low overhead.
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* doesn't have to count over a second.
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*/
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ulong
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perfticks(void)
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{
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uvlong x;
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if(m->havetsc)
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cycles(&x);
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else
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x = 0;
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return x;
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}
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2020-11-29 16:43:22 +00:00
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PCArch archgeneric = {
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.id= "generic",
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.ident= 0,
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.reset= archreset,
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.intrinit= i8259init,
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.intrassign= i8259assign,
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.intrirqno= i8259irqno,
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.intrvecno= i8259vecno,
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.intrspurious= i8259isr,
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.intron= i8259on,
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.introff= i8259off,
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2021-01-17 20:21:12 +00:00
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.clockinit= i8253init,
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2020-11-29 16:43:22 +00:00
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.clockenable= i8253enable,
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.fastclock= i8253read,
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.timerset= i8253timerset,
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};
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