120 lines
2.6 KiB
Plaintext
120 lines
2.6 KiB
Plaintext
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.TH GETFCR 2
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.SH NAME
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getfcr, setfcr, getfsr, setfsr \- control floating point
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.SH SYNOPSIS
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.B #include <u.h>
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.br
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.B #include <libc.h>
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.PP
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.B
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ulong getfcr(void)
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.PP
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.B
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void setfcr(ulong fcr)
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.PP
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.B
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ulong getfsr(void)
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.PP
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.B
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void setfsr(ulong fsr)
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.SH DESCRIPTION
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These routines provide a fairly portable interface to control the
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rounding and exception characteristics of IEEE 754 floating point units.
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In effect, they define a pair of pseudo-registers, the floating
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point control register,
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.BR fcr ,
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which affects rounding, precision, and exceptions, and the
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floating point status register,
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.BR fsr ,
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which holds the accrued exception bits.
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Each register has a
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.I get
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routine to retrieve its value, a
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.I set
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routine to modify it,
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and macros that identify its contents.
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.PP
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The
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.B fcr
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contains bits that, when set, halt execution upon exceptions:
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.B FPINEX
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(enable inexact exceptions),
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.B FPOVFL
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(enable overflow exceptions),
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.B FPUNFL
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(enable underflow exceptions),
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.B FPZDIV
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(enable zero divide exceptions), and
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.B FPINVAL
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(enable invalid operation exceptions).
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Rounding is controlled by installing in
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.BR fcr ,
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under mask
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.BR FPRMASK ,
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one of the values
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.B FPRNR
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(round to nearest),
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.B FPRZ
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(round towards zero),
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.B FPRPINF
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(round towards positive infinity), and
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.B FPRNINF
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(round towards negative infinity).
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Precision is controlled by installing in
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.BR fcr ,
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under mask
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.BR FPPMASK ,
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one of the values
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.B FPPEXT
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(extended precision),
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.B FPPSGL
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(single precision), and
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.B FPPDBL
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(double precision).
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.PP
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The
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.B fsr
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holds the accrued exception bits
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.BR FPAINEX ,
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.BR FPAOVFL ,
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.BR FPAUNFL ,
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.BR FPAZDIV ,
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and
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.BR FPAINVAL ,
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corresponding to the
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.B fsr
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bits without the
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.B A
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in the name.
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.PP
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Not all machines support all modes. If the corresponding mask
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is zero, the machine does not support the rounding or precision modes.
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On some machines it is not possible to clear selective accrued
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exception bits; a
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.I setfsr
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clears them all.
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The exception bits defined here work on all architectures.
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Where possible, the initial state is equivalent to
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.IP
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.EX
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setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL);
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.EE
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.PP
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However, this may vary between architectures:
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the default is to provide what the hardware does most efficiently.
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Use these routines
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if you need guaranteed behavior.
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Also, gradual underflow is not available on some machines.
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.SH EXAMPLE
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To enable overflow traps and make sure registers are rounded
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to double precision (for example on the MC68020, where the
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internal registers are 80 bits long):
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.EX
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.IP
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.ft L
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setfcr((getfcr() & ~FPPMASK) | FPPDBL | FPOVFL);
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.ft
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.EE
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.SH SOURCE
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.B /sys/src/libc/$objtype/getfcr.s
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